| 1325 | -- | 1336 | Subhasis Laha, Janak H. Patel, Ravishankar K. Iyer. Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems |
| 1337 | -- | 1352 | Clyde P. Kruskal, Marc Snir, Alan Weiss. The Distribution of Waiting Times in Clocked Multistage Interconnection Networks |
| 1353 | -- | 1365 | Dalibor F. Vrsalovic, Daniel P. Siewiorek, Zary Segall, Edward F. Gehringer. Performance Prediction and Calibration for a Class of Multiprocessors |
| 1366 | -- | 1374 | David Bernstein, Haran Boral, Ron Y. Pinter. Optimal Chaining in Expression Trees |
| 1375 | -- | 1383 | Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura. High-Speed CAM-Based Architecture for a Prolog Machine (ASCA) |
| 1384 | -- | 1397 | Virginia Mary Lo. Heuristic Algorithms for Task Assignment in Distributed Systems |
| 1398 | -- | 1410 | Adit D. Singh. Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays |
| 1411 | -- | 1414 | Peter C. Maxwell. Comparative Analysis of Different Implementations of Multiple-Input Signature Analyzers |
| 1414 | -- | 1418 | Jerzy Tyszer. A Multiple Fault-Tolerant Processor Network Architecture for Pipeline Computing |
| 1419 | -- | 1422 | Henryk Krawczyk, Wojciech E. Kozlowski. On the Diagnosability of Multicomputer Systems with Homogeneous and Incomplete Tests |
| 1422 | -- | 1425 | Uwe Schwiegelshohn, Lothar Thiele. A Systolic Array for the Assignment Problem |
| 1426 | -- | 1428 | Petra De Jong, A. J. van de Goor. Test Pattern Generation for API Faults in RAM |
| 1428 | -- | 1434 | Ferng-Ching Lin, I-Chen Wu. Broadcast Normalization in Systolic Design |
| 1434 | -- | 1438 | Franklin T. Luk, Haesun Park. Fault-Tolerant Matrix Triangularizations on Systolic Arrays |
| 1438 | -- | 1442 | Wen-Tsuen Chen, Jang-Ping Sheu. Performance Analysis of Multistage Interconnection Networks with Hierarchical Requesting Model |
| 1442 | -- | 1445 | Yoshinori Yamamoto, Shiro Fujita. Relationship Between ::::P::::-Valued Majority Functions and ::::P::::-Valued Threshold Functions |
| 1445 | -- | 1450 | Kyungsook Y. Lee, Wael Hegazy. The Extra Stage Gamma Network |
| 1450 | -- | 1454 | Nikolaos Gaitanis. The Design of Totally Self-Checking TMR Fault-Tolerant Systems |
| 1454 | -- | 1458 | Ahmed K. Elmagarmid, Ajoy Kumar Datta. Two-Phase Deadlock Detection Algorithm |
| 1459 | -- | 1461 | Nathalie Homobono, Claudine Peyrat. Connectivity of Imase and Itoh Digraphs |
| 1461 | -- | 1465 | S. Aborhey. Binary Decision Tree Test Functions |
| 1465 | -- | 1467 | Kang G. Shin, Parameswaran Ramanathan. Transmission Delays in Hardware Clock Synchronization |
| 1468 | -- | 1470 | David B. Skillicorn. A New Class of Fault-Tolerant Static Interconnection Networks |
| 1470 | -- | 1476 | Behrooz Parhami. Carry-Free Addition of Recorded Binary Signed-Digit Numbers |
| 1476 | -- | 1480 | Che-Liang Yang, Gerald M. Masson. A Distributed Algorithm for Fault Diagnosis in Systems with Soft Failures |
| 1480 | -- | 1484 | Donatella Sciuto, Fabrizio Lombardi. On Functional Testing of Array Processors |