Abstract is missing.
- Determination of Yield Bounds Prior to RoutingArunshankar Venkataraman, Israel Koren. 4-13 [doi]
- Impact of Simulation Parameters on Critical Area AnalysisJulie D. Segal, Sergei Bakarian, Ron Ross. 14 [doi]
- Creating 35 mm Camera Active Pixel SensorsGlenn H. Chapman, Yves Audet. 22-30 [doi]
- Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAMMarkus Rudack, Dirk Niggemeyer. 31-39 [doi]
- Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI SystemsNobuhiro Tomabechi. 40-45 [doi]
- Limitations to Estimating Yield Based on In-Line Defect MeasurementsStuart L. Riley. 46-54 [doi]
- Yield Estimation of VLSI Circuits with Downscaled LayoutsWitold A. Pleskacz. 55-60 [doi]
- Automatic Detection of Spatial Signature on Wafermaps in a High Volume ProductionFrederic Duvivier. 61 [doi]
- 8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS DefectsJames F. Plusquellic, Amy Germida, Zheng Yan. 68-76 [doi]
- Charge Sharing Fault Detection for CMOS Domino Logic CircuitsChing-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone. 77-85 [doi]
- Testing for Path Delay Faults Using Test PointsSpyros Tragoudas, N. Denny. 86-94 [doi]
- A Zero Aliasing Built-In Self Test Technique for Delay Fault TestingY. Tsiatouhas, Th. Haniotakis. 95-100 [doi]
- Low-Cost Test for Large Analog IC sSule Ozev, Alex Orailoglu. 101 [doi]
- Novel Control Pattern Generators for Interconnect Testing with Boundary ScanWenyi Feng, Fred J. Meyer, Fabrizio Lombardi. 112-120 [doi]
- Low Power Dissipation in BIST Schemes for Modified Booth MultipliersXrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou. 121-129 [doi]
- LFSR/SR Pseudo-Exhaustive TPG in Fewer Test CyclesDimitrios Kagaris, Spyros Tragoudas. 130-138 [doi]
- Power Characterization of LFSRsMarco Brazzarola, Franco Fummi. 139-147 [doi]
- Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power ReductionXiaodong Zhang, Kaushik Roy. 148 [doi]
- Failure Tests on 64 Mb SDRAM in Radiation EnvironmentStefano Bertazzoni, Gian-Carlo Cardarilli, D. Piergentili, Marcello Salmeri, Adelio Salsano, Domenico Di Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. de Francesco, P. G. Picozza, A. Rovelli. 158-164 [doi]
- RAMSES: A Fast Memory Fault SimulatorChi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu. 165-173 [doi]
- Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis InformationMarco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi. 174-180 [doi]
- Fast Signature Simulation for PPSFP SimulatorsFiras Khadour, Xiaoling Sun. 181 [doi]
- Stratified Testing of Multichip Module Systems under Uneven Known-Good-YieldNohpill Park, Fabrizio Lombardi. 192-200 [doi]
- Testable and Fault Tolerant Design for FFT NetworksJin-Fu Li, Cheng-Wen Wu. 201-209 [doi]
- Soft-Error Detection through Software Fault-Tolerance TechniquesMaurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante. 210-218 [doi]
- Optimal Vector Selection for Low Power BISTFulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante. 219-226 [doi]
- A Structural Approach for Space Compaction for Sequential CircuitsMarkus Seuring, Michael Gössel. 227 [doi]
- A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAsParag K. Lala, Anup Singh, Alvernon Walker. 238-246 [doi]
- A Synthesis Methodology Aimed at Improving the Quality of TSC DevicesCristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice. 247-255 [doi]
- Power Consumption in Fast Dividers Using Time Shared TMRW. Lynn Gallagher, Earl E. Swartzlander Jr.. 256-264 [doi]
- Time-Shared Modular Redundancy for Fault-Tolerant FFT ProcessorsVincenzo Piuri, Earl E. Swartzlander Jr.. 265-273 [doi]
- Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAsMonica Alderighi, Sergio D Angelo, Giacomo R. Sechi, Vincenzo Piuri. 274 [doi]
- Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction CapabilityKiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara. 284-292 [doi]
- Erasure Error Correction with Hardware DetectionWilliam D. Armitage, Jien-Chung Lo. 293-301 [doi]
- Design of Fault-Tolerant Solid State Mass MemoryGian-Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci. 302-310 [doi]
- Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data RetentionYasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu. 311-318 [doi]
- Cost Models for Large File Memory DRAMs with ECC and Bad Block MarkingC. Wickman, Duncan G. Elliott, Bruce F. Cockburn. 319 [doi]
- Transient and Permanent Fault Diagnosis for FPGA-Based TMR SystemsSergio D Angelo, Giacomo R. Sechi, Cecilia Metra. 330-338 [doi]
- A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test PathsYiorgos Makris, Alex Orailoglu. 339-347 [doi]
- Good Processor Identification in Two-Dimensional GridsFred J. Meyer, Fabrizio Lombardi, Jun Zhao. 348-356 [doi]
- A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error WaveformsSasikumar Cherubal, Abhijit Chatterjee. 357 [doi]
- Reconfiguration of One-Time Programmable FPGAs with Faulty Logic ResourcesWenyi Feng, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi. 368-376 [doi]
- Defect and Fault Tolerance FPGAs by Shifting the Configuration DataAbderrahim Doumar, Satoshi Kaneko, Hideo Ito. 377-385 [doi]
- Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA ArchitecturesJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak. 386-394 [doi]
- Reconfiguration of Two-Dimensional Meshes Embedded in Faulty HypercubesSumito Nakano, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui. 395-403 [doi]