David B. Whalley - researchr alias

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2010

Improving both the performance benefits and speed of optimization phase sequence searchesPrasad Kulkarni, Michael R. Jantz, David B. Whalley. lctrts 2010: 95-104 [doi]

Parametric timing analysis and its application to dynamic voltage scalingSibin Mohan, Frank Mueller, Michael Root, William Hawkins, Christopher A. Healy, David B. Whalley, Emilio Vivancos. tecs, 10(2):25, 2010. [doi]

2009

2008

2007

High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, ProceedingsKoen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer, editors, Volume 4367 of Lecture Notes in Computer Science, Springer, 2007.

Generalizing parametric timing analysisJoel Coffman, Christopher A. Healy, Frank Mueller, David B. Whalley. lctrts 2007: 152-154 [doi]

Addressing instruction fetch bottlenecks by using an instruction register fileStephen Roderick Hines, Gary S. Tyson, David B. Whalley. lctrts 2007: 165-174 [doi]

Guaranteeing Hits to Improve the Efficiency of a Small Instruction CacheStephen Hines, David B. Whalley, Gary S. Tyson. micro 2007: 433-444 [doi]

Fast, accurate design space exploration of embedded systems memory configurationsJason Hiser, Jack W. Davidson, David B. Whalley. SAC 2007: 699-706 [doi]

Evaluating Heuristic Optimization Phase Order Search AlgorithmsPrasad Kulkarni, David B. Whalley, Gary S. Tyson. CGO 2007: 157-169 [doi]

Guest EditorialDavid B. Whalley. tecs, 6(1), 2007. [doi]

Facilitating compiler optimizations through the dynamic mapping of alternate register structuresChris Zimmer, Stephen Roderick Hines, Prasad Kulkarni, Gary S. Tyson, David B. Whalley. cases 2007: 165-169 [doi]

2006

Adapting compilation techniques to enhance the packing of instructions into registersStephen Hines, David B. Whalley, Gary S. Tyson. cases 2006: 43-53 [doi]

Reducing the cost of conditional transfers of control by using comparison specificationsWilliam C. Kreahling, Stephen Hines, David B. Whalley, Gary S. Tyson. lctrts 2006: 64-71 [doi]

VISTA: VPO interactive system for tuning applicationsPrasad Kulkarni, Wankang Zhao, Stephen Hines, David B. Whalley, Xin Yuan, Robert van Engelen, Kyle Gallivan, Jason Hiser, Jack W. Davidson, Baosheng Cai, Mark W. Bailey, Hwashin Moon, Kyunghwan Cho, Yunheung Paek. tecs, 5(4):819-863, 2006. [doi]

Exhaustive Optimization Phase Order Space ExplorationPrasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson. CGO 2006: 306-318 [doi]

In search of near-optimal optimization phase orderingsPrasad Kulkarni, David B. Whalley, Gary S. Tyson, Jack W. Davidson. lctrts 2006: 83-92 [doi]

Improving WCET by applying worst-case path optimizationsWankang Zhao, William C. Kreahling, David B. Whalley, Christopher A. Healy, Frank Mueller. rts, 34(2):129-152, 2006. [doi]

2005

Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindowsStephen Hines, Gary S. Tyson, David B. Whalley. euromicro 2005: 19-29 [doi]

Improving Program Efficiency by Packing Instructions into RegistersStephen Hines, Joshua Green, Gary S. Tyson, David B. Whalley. isca 2005: 260-271 [doi]

Using de-optimization to re-optimize codeStephen Hines, Prasad Kulkarni, David B. Whalley, Jack W. Davidson. emsoft 2005: 114-123 [doi]

Branch elimination by condition mergingWilliam C. Kreahling, David B. Whalley, Mark W. Bailey, Xin Yuan, Gang-Ryung Uh, Robert van Engelen. SPE, 35(1):51-74, 2005. [doi]

Fast and efficient searches for effective optimization-phase sequencesPrasad Kulkarni, Stephen Hines, David B. Whalley, Jason Hiser, Jack W. Davidson, Douglas L. Jones. taco, 2(2):165-198, 2005. [doi]

ParaScale: Exploiting Parametric Timing Analysis for Real-Time Schedulers and Dynamic Voltage ScalingSibin Mohan, Frank Mueller, William Hawkins, Michael Root, Christopher A. Healy, David B. Whalley. rtss 2005: 233-242 [doi]

Timing Analysis for Sensor Network Nodes of the Atmega Processor FamilySibin Mohan, Frank Mueller, David B. Whalley, Christopher A. Healy. rtas 2005: 405-414 [doi]

Compiler transformations for effectively exploiting a zero overhead loop bufferGang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Yunheung Paek, Vincent Cao, Chris Burns. SPE, 35(4):393-412, 2005. [doi]

Tuning High Performance Kernels through Empirical CompilationR. Clint Whaley, David B. Whalley. icpp 2005: 89-98 [doi]

Improving WCET by applying a WC code-positioning optimizationWankang Zhao, David B. Whalley, Christopher A. Healy, Frank Mueller. taco, 2(4):335-365, 2005. [doi]

Improving WCET by Optimizing Worst-Case PathsWankang Zhao, William C. Kreahling, David B. Whalley, Christopher A. Healy, Frank Mueller. rtas 2005: 138-147 [doi]

2004

2003

2002

2001

2000

1999

Bounding Pipeline and Instruction Cache PerformanceChristopher A. Healy, Robert D. Arnold, Frank Mueller, David B. Whalley, Marion G. Harmon. TC, 48(1):53-70, 1999. [doi]

Tighter Timing Predictions by Automatic Detection and Exploitation of Value-Dependent ConstraintsChristopher A. Healy, David B. Whalley. rtas 1999: 79-88 [doi]

Timing Constraint Specification and AnalysisLo Ko, Naghan Al-Yaqoubi, Christopher A. Healy, Emily Ratliff, Robert D. Arnold, David B. Whalley, Marion G. Harmon. SPE, 29(1):77-98, 1999.

Improving memory hierarchy performance for irregular applicationsJohn M. Mellor-Crummey, David B. Whalley, Ken Kennedy. ics 1999: 425-433 [doi]

Effectively Exploiting Indirect JumpsGang-Ryung Uh, David B. Whalley. SPE, 29(12):1061-1101, 1999.

Effective Exploitation of a Zero Overhead Loop BufferGang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanjay Jinturkar, Chris Burns, Vincent Cao. lctrts 1999: 10-19 [doi]

Timing Analysis for Data and Wrap-Around Fill CachesRandall T. White, Frank Mueller, Christopher A. Healy, David B. Whalley, Marion G. Harmon. rts, 17(2-3):209-233, 1999.

1998

Bounding Loop Iterations for Timing AnalysisChristopher A. Healy, Mikael Sjödin, Viresh Rustagi, David B. Whalley. rtas 1998: 12-21 [doi]

Improving Performance by Branch ReorderingMinghui Yang, Gang-Ryung Uh, David B. Whalley. PLDI 1998: 130-141

1997

Coalescing Conditional Branches into Efficient Indirect JumpsGang-Ryung Uh, David B. Whalley. SAS 1997: 315-329

Timing Analysis for Data Caches and Set-Associative CachesRandall T. White, Christopher A. Healy, David B. Whalley, Frank Mueller, Marion G. Harmon. rtas 1997: 192-202 [doi]

1996

Supporting the specification and analysis of timing constraintsLo Ko, Christopher A. Healy, Emily Ratliff, Robert D. Arnold, David B. Whalley, Marion G. Harmon. rtas 1996: 170 [doi]

1995

1994

1993

Isolation and Analysis of Optimization ErrorsMickey R. Boyd, David B. Whalley. PLDI 1993: 26-35

Techniques for Fast Instruction Cache Performance EvaluationDavid B. Whalley. SPE, 23(1):95-118, 1993.

1992

Relating Static and Dynamic Machine Code MeasurementsJack W. Davidson, John R. Rabung, David B. Whalley. TC, 41(4):444-454, 1992.

A Retargetable Technique for Predicting Execution TimeMarion G. Harmon, Theodore P. Baker, David B. Whalley. rtss 1992: 68-77 [doi]

Avoiding Unconditional Jumps by Code ReplicationFrank Mueller, David B. Whalley. PLDI 1992: 322-330

Fast Instruction Cache Performance Evaluation Using Compile-Time AnalysisDavid B. Whalley. sigmetrics 1992: 13-22

1991

Methods for Saving and Restoring Register Values across Function CallsJack W. Davidson, David B. Whalley. SPE, 21(2):149-165, 1991.

1990

Reducing the Cost of Branches by Using RegistersJack W. Davidson, David B. Whalley. isca 1990: 182-191

Ease: An Environment for Architecture Study and ExperimentationJack W. Davidson, David B. Whalley. sigmetrics 1990: 259-260 [doi]

1989

Quick Compilers Using Peephole OptimizationJack W. Davidson, David B. Whalley. SPE, 19(1):79-97, 1989.