Gary William Grewal - researchr alias

researchr

You are not signed in
Sign in
Sign up

Viewing Publication 1 - 33 from 33

2023

FPGA Placement: Dynamic Decision Making Via Machine LearningTimothy Martin, Charlotte Barnes, Gary William Grewal, Shawki Areibi. sbcci 2023: 1-6 [doi]

A Deterministic Parallel Routing Approach for Accelerating Pathfinder-based AlgorithmsUmair F. Siddiqi, Gary William Grewal, Shawki Areibi. vlsi 2023: 1-6 [doi]

2022

Integrating Machine-Learning Probes into the VTR FPGA Design FlowTimothy Martin, C. Barnes, Gary William Grewal, Shawki Areibi. sbcci 2022: 1-6 [doi]

2020

Machine Learning for Congestion Management and Routability Prediction within FPGA PlacementHannah Szentimrey, Abeer Y. Al-Hyari, Jérémy Foxcroft, Timothy Martin, David Noel, Gary William Grewal, Shawki Areibi. todaes, 25(5), 2020. [doi]

2018

Corrigendum to "An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization"Omar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal. ijrc, 2018, 2018. [doi]

2017

A Machine Learning Framework for FPGA Placement (Abstract Only)Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao. fpga 2017: 286 [doi]

2016

An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable SystemsAhmed Al-Wattar, Shawki Areibi, Gary William Grewal. ijrc, 2016, 2016. [doi]

Historical Data Integration a Study of WWI Canadian SoldiersLuiza Antonie, Harshavardhan Gadgil, Gary William Grewal, Kris Inwood. icdm 2016: 186-193 [doi]

2015

Efficient Mapping and Allocation of Execution Units to Task Graphs using an Evolutionary FrameworkAhmed Al-Wattar, Shawki Areibi, Gary William Grewal. sigarch, 43(4):46-51, 2015. [doi]

Scalable analytic placement for FPGA on GPGPURyan Pattison, Christian Fobel, Gary William Grewal, Shawki Areibi. reconfig 2015: 1-6 [doi]

2014

2013

An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain OptimizationOmar Ahmed, Shawki Areibi, Robert Collier, Gary William Grewal. ijrc, 2013, 2013. [doi]

Hardware Accelerators Targeting a Novel Group Based Packet Classification AlgorithmOmar Ahmed, Shawki Areibi, Gary William Grewal. ijrc, 2013, 2013. [doi]

2012

Depictions of genotypic space for evaluating the suitability of different recombination operatorsRobert Collier, Christian Fobel, Gary William Grewal, Mark Wineberg. gecco 2012: 609-616 [doi]

An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-CMaxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi. vlsi, 2012, 2012. [doi]

2010

An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computersEd Armstrong, Gary William Grewal, Shawki Areibi, Gerarda Darlington. ccece 2010: 1-6 [doi]

Hardware acceleration of Scatter SearchMaxwell Walton, Gary William Grewal, Gerarda Darlington. ieeehpcs 2010: 436-443 [doi]

2006

Clustering Hanan Points to Reduce Vlsi Interconnect Routing TimesShouvik Chowdhury, Gary William Grewal, Dilip K. Banerji. ccece 2006: 1223-1227 [doi]

2004

A Fast Hierarchical Approach to FPGA PlacementPeng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji. csreaESA 2004: 497-503

An Approximate Solution for Steiner Trees in Multicast RoutingGary William Grewal, Ming Xu, Charlie Obimbo. icai 2004: 707-711

Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner TreesGary William Grewal, Thomas Charles Wilson, Ming Xu, Dilip K. Banerji. vlsid 2004: 855-862 [doi]

2003

Mapping Reference Code to Irregular DSPS within the Retargetable, Optimizing Compiler Cogen(T)Gary William Grewal, Thomas Charles Wilson. ijcia, 3(1):45-64, 2003. [doi]

Hierarchical Genetic Algorithms Applied to Datapath SynthesisGary William Grewal, Mike O Cleirigh, Charlie Obimbo. icai 2003: 994-1002

2002

An Enhanced Genetic Algorithm Approach to the Channel Assignment Problem in Mobile Cellular NetworksGary William Grewal, Thomas Charles Wilson, Christopher W. Nell. ai 2002: 325-333 [doi]

2001

Mapping reference code to irregular DSPs within the retargetable, optimizing compiler COGEN(T)Gary William Grewal, Thomas Charles Wilson. euromicro 2001: 192-202 [doi]

An Enhanced Genetic Algorithm for Solving the High-Level Synthesis Problems of Scheduling, Allocation, and BindingGary William Grewal, Thomas Charles Wilson. ijcia, 1(1):91-110, 2001.

1997

An Enhanced Genetic Solution for Scheduling, Module Allocation, and Binding in VLSI DesignGary William Grewal, Thomas Charles Wilson. vlsid 1997: 51-56 [doi]

Shake And Bake: A Method of Mapping Code to Irregular DSPsThomas Charles Wilson, Gary William Grewal. vlsid 1997: 506-508 [doi]

1996

A Global Mode Instruction Minimization Technique for Embedded DSPsGary William Grewal. glvlsi 1996: 18 [doi]

1994

An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block SynthesisThomas Charles Wilson, Gary William Grewal, Dilip K. Banerji. iccd 1994: 581-586

An ILP-based approach to code generationThomas Charles Wilson, Gary William Grewal, Shawn Henshall, Dilip K. Banerji. Dagstuhl 1995: 103-118

Sign in or sign up to see more results.

runs on WebDSL