Serge Weber - researchr alias

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Viewing Publication 1 - 49 from 49

2023

A Transformer Neural Network For AC series arc-fault detectionAlexis Chabert, Mohamed Chafik Bakkay, Patrick Schweitzer, Serge Weber, Jonathan Andrea. eaai, 125:106651, 2023. [doi]

2022

State-Space Simulation of Electric Arc FaultsAlexis Chabert, Patrick Schweitzer, Serge Weber, Jonathan Andrea. taes, 58(3):1650-1659, 2022. [doi]

2020

Scalable, dynamic and growing hardware self-organizing architecture for real-time vector quantizationSlavisa Jovanovic, Hassan Rabah, Serge Weber, Khaled Ben Khalifa, Mohamed Hédi Bedoui. icecsys 2020: 1-4 [doi]

2019

A Multi-Application, Scalable and Adaptable Hardware SOM ArchitectureMehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui. ijcnn 2019: 1-8 [doi]

AC series arc fault detection with stacked autoencodersHien Duc Vu, Edwin Calderon, Patrick Schweitzer, Serge Weber, Nicolas Britsch. iecon 2019: 4606-4609 [doi]

2018

A scalable and adaptable hardware NoC-based self organizing mapMehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui. mam, 57:1-14, 2018. [doi]

High performance scalable hardware SOM architecture for real-time vector quantizationSlavisa Jovanovic, Hassan Rabah, Serge Weber. ipas2 2018: 256-261 [doi]

2016

A Scalable Flexible SOM NoC-Based Hardware ArchitectureMehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hédi Bedoui. wsom 2016: 165-175 [doi]

A hardware configurable self-organizing map for real-time color quantizationMehdi Abadi, Slavisa Jovanovic, Khaled Ben Khalifa, Serge Weber, Mohamed Hedi Bedoui. icecsys 2016: 336-339 [doi]

2014

A Novel Framework for the Design of Adaptable Reconfigurable Partitions for the Placement of Variable-sized IP CoresNicolas Marques, Hassan Rabah, Eric Dabellani, Serge Weber. esl, 6(3):45-48, 2014. [doi]

2013

2012

An approach: FPGA based dynamically reconfigurable architecture to enable several scheme controls for power convertersEber Espino Garibay, Domingo Torres, Serge Weber. iceee 2012: 1-6 [doi]

2011

An efficient VLSI implementation of H.264/AVC intra-frame transcoderMichael Guarisco, Eric Dabellani, Nicolas Marques, Hassan Rabah, Yves Berviller, Serge Weber. icecsys 2011: 1-4 [doi]

Efficient reconfigurable entropy coder for embedded multi-standards video adaptationNicolas Marques, Hassan Rabah, Eric Dabellani, Serge Weber. cvpr 2011: 144-149 [doi]

2009

2008

A new high-performance scalable dynamic interconnection for FPGA-based reconfigurable systemsSlavisa Jovanovic, Camel Tanougast, Serge Weber. asap 2008: 61-66 [doi]

A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable SystemsSlavisa Jovanovic, Camel Tanougast, Serge Weber. arc 2008: 159-170 [doi]

A framework of architectural synthesis for dynamically reconfigurable FPGAsTing Liu, Camel Tanougast, Serge Weber. socc 2008: 283-286 [doi]

VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream CipherCamel Tanougast, Serge Weber, Gilles Millerioux, Jamal Daafouz, Ahmed Bouridane. delta 2008: 386-389 [doi]

An Auto-adaptation Method for Dynamically Reconfigurable System-on-ChipXun Zhang, Hassan Rabah, Serge Weber. isvlsi 2008: 499-502 [doi]

Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPCXun Zhang, Hassan Rabah, Serge Weber. delta 2008: 153-157 [doi]

2007

A Hardware Preemptive Multitasking Mechanism Based on Scan-path Register Structure for FPGA-based Reconfigurable SystemsSlavisa Jovanovic, Camel Tanougast, Serge Weber. ahs 2007: 358-364 [doi]

CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAsSlavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber. fpl 2007: 753-756 [doi]

A Dynamic Communication Structure for Dynamically Reconfigurable FPGAsSlavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber. recosoc 2007: 98-105

The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm ImplementationOscar Pérez, Yves Berviller, Camel Tanougast, Serge Weber. jucs, 13(3):349-362, 2007. [doi]

An Fpga implementation of the HME self-synchronizing stream cipher for Enhanced security and performanceCamel Tanougast, Serge Weber, Gilles Millerioux, Ahmed Bouridane, Jamal Daafouz. ahs 2007: 110-118 [doi]

Cluster-Based Hybrid Reconfigurable Architecture for Auto-adaptive SoCXun Zhang, Hassan Rabah, Serge Weber. icecsys 2007: 979-982 [doi]

Auto-adaptive reconfigurable architecture for scalable multimedia applicationsXun Zhang, Hassan Rabah, Serge Weber. ahs 2007: 139-145 [doi]

2006

Toward a methodology for optimizing algorithm-architecture adequacy for implementation reconfigurable systemTing Liu, Camel Tanougast, Serge Weber. icecsys 2006: 1085-1088 [doi]

2005

Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysisMichael Janiaut, Camel Tanougast, Hassan Rabah, Yves Berviller, Christian Mannino, Serge Weber. fpl 2005: 386-390

2004

2003

Hardware Partitioning Software for Dynamically Reconfigurable SoC DesignPhilippe Brunet, Camel Tanougast, Yves Berviller, Serge Weber. iwsoc 2003: 106-111 [doi]

Linear array processors with multiple access modes memory for real-time image processingHassan Rabah, Hervé Mathias, Serge Weber, Eril Mozef, Camel Tanougast. rti, 9(3):205-213, 2003. [doi]

Automated RTR Temporal Partitioning for Reconfigurable Embedded Real-Time System DesignCamel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber. ipps 2003: 178 [doi]

A Partitioning Methodology That Optimises the Area on Reconfigurable Real-Time Embedded SystemsCamel Tanougast, Yves Berviller, Serge Weber, Philippe Brunet. ejasp, 2003(6):494-501, 2003. [doi]

Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time systemCamel Tanougast, Yves Berviller, Philippe Brunet, Serge Weber, Hassan Rabah. mam, 27(3):115-130, 2003. [doi]

2002

SOPC-based Embedded Smart Strain Gage SensorSylvain Poussier, Hassan Rabah, Serge Weber. fpl 2002: 1131-1134 [doi]

Linear array processors with multiple access modes memory for real-time image processingHassan Rabah, Hervé Mathias, Eril Mozef, Domingo Torres, Serge Weber. apccas 2002: 203-206 [doi]

2000

Optimization of Motion Estimator for Run-Time-Reconfiguration ImplementationCamel Tanougast, Yves Berviller, Serge Weber. ipps 2000: 959-965 [doi]

1999

SIMD/restricted MIMD parallel architecture for Image Processing Based on a New Design of a Multi-mode Access MemoryDomingo Torres, Hervé Mathias, Hassan Rabah, Serge Weber. pdpta 1999: 567-570

1996

Parallel architecture dedicated to connected component analysisEril Mozef, Serge Weber, Jamal Jaber, Etienne Tisserand. icpr 1996: 699-703 [doi]

LAPCAM, Linear Array of Processors Using Content-Addressable Memories: A New Design of Machine Vision for Parallel Image ComputationsEril Mozef, Serge Weber, Jamal Jaber, Claude Bataille. mva 1996: 166-169 [doi]

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