Tetsuo Hironaka - researchr alias

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Viewing Publication 1 - 30 from 30

2021

Rumpfr: A Fast and Memory Leak-free Rust Binding to the GNU MPFR LibraryTomoya Michinaka, Hideyuki Kawabata, Tetsuo Hironaka. jip, 29:676-684, 2021. [doi]

2019

OSAIFU: A Source Code Factorizer on Android StudioMasahiro Hata, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka. ICSM 2019: 422-425 [doi]

Efficient Searching for Essential API Member Sets based on Inclusion Relation ExtractionYushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka. ijndc, 7(4):149-157, 2019. [doi]

Extracting Inclusion Graphs of API Member Sets to Improve SearchabilityYushi Kondoh, Masashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka. sera 2019: 53-59 [doi]

Resolving Ambiguous Types in Haskell by Checking Uniqueness of Type Variable Assignments under Type Class ConstraintsYuya Kono, Hideyuki Kawabata, Tetsuo Hironaka. jip, 27:87-94, 2019. [doi]

Easy-going Development of Event-Driven Applications by Iterating a Search-Select-Superpose LoopMasashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka. jip, 27:257-267, 2019. [doi]

SAIFU: Supporting Program Understanding by Automatic Indexing of Functionalities in Source CodeMasashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka. ijndc, 7(4):167-174, 2019. [doi]

Supporting Program Understanding by Automatic Indexing of Functionalities in Source CodeMasashi Nishimoto, Keiji Nishiyama, Hideyuki Kawabata, Tetsuo Hironaka. sera 2019: 13-18 [doi]

2018

Traf: A Graphical Proof Tree Viewer Cooperating with Coq Through Proof GeneralHideyuki Kawabata, Yuta Tanaka, Mai Kimura, Tetsuo Hironaka. aplas 2018: 157-165 [doi]

2015

ForewordTetsuo Hironaka. ieicet, 98-D(2):219, 2015. [doi]

2012

A Physical Design Method for a New Memory-Based Reconfigurable Architecture without Switch BlocksMasatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro. ieicet, 95-D(2):324-334, 2012. [doi]

2011

EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable ArchitectureMasatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro. reconfig 2011: 448-454 [doi]

Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip areaKazuya Tanigawa, Tetsuo Hironaka. isocc 2011: 187-190 [doi]

2010

Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable ProcessorKazuya Tanigawa, Ken ichi Umeda, Tetsuo Hironaka. arc 2010: 388-393 [doi]

2008

2007

4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line WordsKoh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka. ieicet, 90-C(11):2157-2160, 2007. [doi]

2006

Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge PipelineKoh Johguchi, Zhaomin Zhu, Hans Jürgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, Kazuya Tanigawa. apccas 2006: 1297-1300 [doi]

Scheduling support hardware for multiprocessor system and its evaluationsTakahiro Sasaki, Tetsuo Hironaka, Naoki Nishimura, Noriyoshi Yoshida. scjapan, 37(2):79-95, 2006. [doi]

2005

2004

Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processorsTetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka. aspdac 2004: 551-552 [doi]

2003

A coarse-grained reconfigurable architecture with low cost configuration data compression mechanismKazuya Tanigawa, Takashi Kawasaki, Tetsuo Hironaka. fpt 2003: 311-314 [doi]

A novel hierarchical multi-port cacheZhaomin Zhu, Koh Johguchi, Hans Jürgen Mattausch, Tetsushi Koide, Tai Hirakawa, Tetsuo Hironaka. esscirc 2003: 405-408 [doi]

2002

A Generalized Execution Model for Programming on Reconfigurable Architectures and an Architecture Supporting the ModelKazuya Tanigawa, Tetsuo Hironaka, Akira Kojima, Noriyoshi Yoshida. fpl 2002: 434-443 [doi]

2000

Prototype microprocessor LSI with scheduling support hardware for operating system on multiprocessor systemNaoki Nishimura, Takahiro Sasaki, Tetsuo Hironaka. aspdac 2000: 29-30 [doi]

Performance Improvements of Thakore s Algorithm with Speculative Execution Technique and Dynamic Task SchedulingTakahiro Sasaki, Tetsuo Hironaka, Seiji Fujino. informaticaSI, 24(1), 2000.

1993

A Micro-Vectorprocessor Architecture: Performance Modeling and BenchmarkingTakashi Hashimoto, Kazuaki Murakami, Tetsuo Hironaka, Hiroto Yasuura. ics 1993: 308-317 [doi]

1992

Benchmarking a vector-processor prototype based on multithreaded streaming/FIFO vector (MSFV) architectureTetsuo Hironaka, Takashi Hashimoto, Keizo Okazaki, Kazuaki Murakami, Shinji Tomita. ics 1992: 272-281 [doi]

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