Abstract is missing.
- Green computing: reducing energy cost and carbon footprint of information processing systemsMassoud Pedram. 1-2 [doi]
- Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systemsJosé Manuel Velasco, David Atienza, Katzalin Olcoz. 3-8 [doi]
- Contact merging algorithm for efficient substrate noise analysis in large scale circuitsEmre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. 9-14 [doi]
- Simultaneous shield and repeater insertionRenatas Jakushokas, Eby G. Friedman. 15-20 [doi]
- Task graph scheduling for reconfigurable architectures driven by reconfigurations hiding and resources reuseMarco D. Santambrogio, Massimo Redaelli, Marco Maggioni. 21-26 [doi]
- Safe clocking for the setup and hold timing constraints in datapath synthesisKeisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki. 27-32 [doi]
- Dynamic context management for low power coarse-grained reconfigurable architectureYoonjin Kim, Rabi N. Mahapatra. 33-38 [doi]
- VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and powerWan-Yu Lee, Iris Hui-Ru Jiang. 39-44 [doi]
- An interconnect-aware delay model for dynamic voltage scaling in NM technologiesHouman Zarrabi, Asim J. Al-Khalili, Yvon Savaria. 45-50 [doi]
- Voltage-island driven floorplanning considering level-shifter positionsBei Yu, Sheqin Dong, Satoshi Goto, Song Chen. 51-56 [doi]
- Design of novel CAM core cell structures for an efficient implementation of low power BCAM systemPalanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas. 57-62 [doi]
- Reducing temperature variability by routing heat pipesKunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker. 63-68 [doi]
- Polynomial coefficient based DC testing of non-linear analog circuitsSuraj Sindia, Virendra Singh, Vishwani D. Agrawal. 69-74 [doi]
- MYGEN: automata-based on-line test generator for assertion-based verificationYann Oddos, Katell Morin-Allory, Dominique Borrione, Marc Boule, Zeljko Zilic. 75-80 [doi]
- An on-chip solution for static ADC test and measurementBrendan Mullane, Ciaran MacNamee, Vincent O Brien, Thomas Fleischmann. 81-86 [doi]
- Multi-level fault modeling for transaction-level specificationsGiovanni Beltrame, Cristiana Bolchini, Antonio Miele. 87-92 [doi]
- Partitioned n-detection test generationIrith Pomeranz, Sudhakar M. Reddy. 93-98 [doi]
- Design tools for emerging technologiesJacob White. 99-100 [doi]
- Soft error rate computation in early design stages using boolean satisfiabilitySyed Z. Shazli, Mehdi Baradaran Tahoori. 101-104 [doi]
- Definition and application of approximate necessary assignmentsIrith Pomeranz, Sudhakar M. Reddy. 105-108 [doi]
- Reducing parity generation latency through input value aware circuitsYusuf Osmanlioglu, Y. Onur Koçberber, Oguz Ergin. 109-112 [doi]
- Multicast routing with dynamic packet fragmentationYoung Hoon Kang, Jeff Sondeen, Jeffrey T. Draper. 113-116 [doi]
- Energy efficient architecture of sensor network node based on compression acceleratorJue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang. 117-120 [doi]
- Towards embedded runtime system level optimization for MPSoCs: on-chip task allocationTheocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar. 121-124 [doi]
- Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chipDaniele Ludovici, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi, Luca Benini. 125-128 [doi]
- On the design of reconfigurable crossbar switch for adaptable on-chip topologies in programmable NoC routersHenrique Cota de Freitas, Philippe Olivier Alexandre Navaux. 129-132 [doi]
- Hierarchical state machine architecture for regular expression pattern matchingCheng-Hung Lin, Hsien-Sheng Hsiao. 133-136 [doi]
- Central vs. distributed dynamic thermal management for multi-core processors: which one is better?Michael Kadin, Sherief Reda, Augustus K. Uht. 137-140 [doi]
- Energy-optimal synchronization primitives for single-chip multi-processorsCesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino. 141-144 [doi]
- Low-power, process-variation tolerant on-chip thermal monitoring using track and hold based thermal sensorsBasab Datta, Wayne P. Burleson. 145-148 [doi]
- A methodology for application-specific NoC architecture generation in a dynamic task structure environmentBalasubramanian Sethuraman, Ranga Vemuri. 149-152 [doi]
- BISM: built-in self map for hybrid crossbar nano-architecturesMehdi Baradaran Tahoori. 153-156 [doi]
- The effects of logic partitioning in a majority logic based CMOS-NANO FPGAHarika Manem, Garrett S. Rose. 157-160 [doi]
- A process variation tolerant self-compensating FinFET based sense amplifier designAarti Choudhary, Sandip Kundu. 161-164 [doi]
- Study of leakage current mechanisms in ballistic deflection transistorsVikas Kaushal, Quentin Diduck, Martin Margala. 165-168 [doi]
- Using soft-edge flip-flops to compensate NBTI-induced delay degradationKarthik Duraisami, Enrico Macii, Massimo Poncino. 169-172 [doi]
- Contradictory antecedent debugging in bounded model checkingDaniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler. 173-176 [doi]
- Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search featureMyeongGyu Jeong, Toru Nakura, Makoto Ikeda, Kunihiro Asada. 177-180 [doi]
- A dual-MOSFET equivalent resistor thermal sensorYongji Jiang, Garrett S. Rose. 181-184 [doi]
- Improved performance and yield with chip master planning design methodologyAli Jahanian, Morteza Saheb Zamani. 185-190 [doi]
- Octilinear redistributive routing in bump arraysRenshen Wang, Chung-Kuan Cheng. 191-196 [doi]
- A stochastic-based efficient critical area extractor on OpenAccess platformBo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan. 197-202 [doi]
- A taylor series methodology for analyzing the effects of process variation on circuit operationRaghuram Srinivasan, Harold W. Carter. 203-208 [doi]
- STI stress aware placement optimization based on geometric programmingJing Li, Bo Yang, Xiaochuan Hu, Qing Dong, Shigetoshi Nakatake. 209-214 [doi]
- Glitch-free design for multi-threshold CMOS NCL circuitsAhmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di. 215-220 [doi]
- Online circuit reliability monitoringBin Zhang. 221-226 [doi]
- Process variation mitigation via post silicon clock tuningKelageri Nagaraj, Sandip Kundu. 227-232 [doi]
- The effect of design parameters on single-event upset sensitivity of MOS current mode logicMahta Haghi, Jeff Draper. 233-238 [doi]
- Varicap threshold logicSamed Maltabas, Martin Margala, Ugur Çilingiroglu. 239-244 [doi]
- Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systemsQi Wu, Jian-Qiang Lu, Kenneth Rose, Tong Zhang. 245-250 [doi]
- High-performance, cost-effective heterogeneous 3D FPGA architecturesRoto Le, Sherief Reda, R. Iris Bahar. 251-256 [doi]
- On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit designRenshen Wang, Chung-Kuan Cheng. 257-262 [doi]
- Power distribution paths in 3-D ICSVasilis F. Pavlidis, Giovanni De Micheli. 263-268 [doi]
- A nine-context programmable optically reconfigurable gate array with semiconductor lasersShinya Kubota, Minoru Watanabe. 269-274 [doi]
- Analysis of challenges for on-chip optical interconnectsRajeev K. Dokania, Alyssa B. Apsel. 275-280 [doi]
- Design challenges in high performance three-dimensional circuitsEby G. Friedman. 281-282 [doi]
- Disruptive technologies and neurally-inspired architecturesPinaki Mazumder. 283-284 [doi]
- Power efficient tree-based crosslinks for skew reductionInna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G. Friedman. 285-290 [doi]
- Dual-threshold pass-transistor logic designLara D. Oliver, Krishnendu Chakrabarty, Hisham Z. Massoud. 291-296 [doi]
- A low-power CMOS thyristor based delay element with programmability extensionsColin J. Ihrig, Gerold Joseph Dhanabalan, Alex K. Jones. 297-302 [doi]
- Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCODhruva Ghai, Saraju P. Mohanty, Elias Kougianos. 303-308 [doi]
- Complementary nano-electromechanical switches for ultra-low power embedded processorsKhawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar. 309-314 [doi]
- A reconfigurable stochastic architecture for highly reliable computingXin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja. 315-320 [doi]
- Bitmask-based control word compression for NISC architecturesChetan Murthy, Prabhat Mishra. 321-326 [doi]
- Better than optimum?: register reduction using idle pipelined functional unitsTaemin Kim, Xun Liu. 327-332 [doi]
- NBTI-aware sleep transistor design for reliable power-gatingAndrea Calimera, Enrico Macii, Massimo Poncino. 333-338 [doi]
- Accelerating multi-party scheduling for transaction-level modelingDi Wang, Vyas Venkataraman, Zhen Wang, Wei Qin, Hangsheng Wang, Mrinal Bose, Jayanta Bhadra. 339-344 [doi]
- Spatial and temporal design debug using partial MaxSATYibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques Silva. 345-350 [doi]
- An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAsTaiga Takata, Yusuke Matsunaga. 351-356 [doi]
- Robust window-based multi-node technology-independent logic minimizationJeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri. 357-362 [doi]
- Timing-driven N-way decompositionDavid Bañeres, Jordi Cortadella, Michael Kishinevsky. 363-368 [doi]
- Deflecting crosstalk by routing reconsideration through refined signal correlation estimationMingjing Chen, Alex Orailoglu. 369-374 [doi]
- Computing with field-coupled nanomagnetsWolfgang Porod. 375-376 [doi]
- Buffer design and optimization for lut-based structured ASIC design stylesPo-Yang Hsu, Shu-Ting Lee, Fu-Wei Chen, Yi-Yu Liu. 377-380 [doi]
- A ubiquitous processor embedded with progressive cipher pipelinesMasa-Aki Fukase, Atsuko Yokoyama, Tomoaki Sato. 381-384 [doi]
- Impact of lithography-friendly circuit layoutPratik J. Shah, Jiang Hu. 385-388 [doi]
- A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnectsMarshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma. 389-392 [doi]
- Dynamic thermal-aware scheduling on chip multiprocessor for soft real-time systemJin Cui, Douglas L. Maskell. 393-396 [doi]
- Enhancing SAT-based sequential depth computation by pruning search spaceYung-Chih Chen, Chun-Yao Wang. 397-400 [doi]
- RDL pre-assignment routing for flip-chip designsJin-Tai Yan, Zhi-Wei Chen. 401-404 [doi]
- A novel mechanism to dynamically switch speed and accuracy in systemC based transaction level modelsZhu Zhou, Dharmin Parikh, Pradnyesh Gudadhe, Arunabha Sen. 405-408 [doi]
- Redundant wire insertion for yield improvementJin-Tai Yan, Zhi-Wei Chen. 409-412 [doi]
- Incremental buffer insertion and module resizing algorithm using geometric programmingQing Dong, Bo Yang, Jing Li, Shigetoshi Nakatake. 413-416 [doi]
- Enhancing bug hunting using high-level symbolic simulationHong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui Chang, Sy-Yen Kuo. 417-420 [doi]
- Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devicesDario Cozzi, Claudia Farè, Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. 421-424 [doi]
- Physical unclonable function and true random number generator: a compact and scalable implementationAbhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont. 425-428 [doi]
- Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channelsYanjie Peng, Andrew G. Klein, Xinming Huang. 429-432 [doi]
- A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmeticSohan Purohit, Sai Rahul Chalamalasetti, Martin Margala. 433-436 [doi]
- A picosecond TDC architecture for multiphase PLLsYifei Luo, Gang Chen, Kuan Zhou. 437-440 [doi]
- Low power and high performance sram design using bank-based selective forward body biasKalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri. 441-444 [doi]
- High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithmYang Sun, Joseph R. Cavallaro. 445-450 [doi]
- High-throughput low-complexity MIMO detector based on K-best algorithmNariman Moezzi Madani, William Rhett Davis. 451-456 [doi]
- Hardware-accelerated gradient noise for graphicsJosef B. Spjut, Andrew E. Kensler, Erik Brunvand. 457-462 [doi]
- Reconfigurable SAD tree architecture based on adaptive sub-sampling in HDTV applicationYiqing Huang, Qin Liu, Satoshi Goto, Takeshi Ikenaga. 463-468 [doi]
- Router with centralized buffer for network-on-chipLing Wang, Jianwen Zhang, Xiaoqing Yang, Dongxin Wen. 469-474 [doi]
- Dynamic reconfiguration approach for high speed turbo decoding using circular ringsImran Ahmed, Cheran Vithanage. 475-480 [doi]
- A switchable PLL frequency synthesizer and hot carrier effectsYang Liu, Ashok Srivastava, Yao Xu. 481-486 [doi]
- On process variation tolerant low cost thermal sensor design in 32nm CMOS technologySpandana Remarsu, Sandip Kundu. 487-492 [doi]
- New performance/power/area efficient, reliable full adder designSohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello. 493-498 [doi]
- Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH codingShu Li, Tong Zhang. 499-504 [doi]
- DX-compactor: distributed X-compaction for SoCsReshma C. Jumani, Niraj Bharatkumar Jain, Virendra Singh, Kewal K. Saluja. 505-510 [doi]
- Reliability aware NoC router architecture using input channel buffer sharingMohammad Hossein Neishaburi, Zeljko Zilic. 511-516 [doi]
- A power-effective scan architecture using scan flip-flops clustering and post-generation fillingZhen Chen, Dong Xiang, Boxue Yin. 517-522 [doi]
- State persistence: a property for guiding test generationIrith Pomeranz, Sudhakar M. Reddy. 523-528 [doi]
- A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuitsAlodeep Sanyal, Abhisek Pan, Sandip Kundu. 529-534 [doi]
- Intracortical wireless microsystems for biosensing and neurostimulationMohamad Sawan. 535-536 [doi]
- Terahertz sensing technologyMichael S. Shur. 537-538 [doi]
- Circuits with light at the nanoscale: meta-nanocircuits and metactronicsNader Engheta. 539-540 [doi]