Abstract is missing.
- Asymptotic probability extraction for non-normal distributions of circuit performanceXin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi. 2-9 [doi]
- Statistical design and optimization of SRAM cell for yield enhancementSaibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy. 10-13 [doi]
- Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxationDebjit Sinha, Hai Zhou. 14-19 [doi]
- Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimizationJinfeng Liu, Pai H. Chou. 21-28 [doi]
- Dynamic voltage and frequency scaling under a precise energy model considering variable and fixed components of the system power dissipationKihwan Choi, Wonbok Lee, Ramakrishna Soma, Massoud Pedram. 29-34 [doi]
- The effects of energy management on reliability in real-time embedded systemsDakai Zhu, Rami G. Melhem, Daniel Mossé. 35-40 [doi]
- DAG-aware circuit compression for formal verificationPer Bjesse, Arne Borälv. 42-49 [doi]
- Dynamic transition relation simplification for bounded property checkingAndreas Kuehlmann. 50-57 [doi]
- Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraintsZurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna. 58-65 [doi]
- Checking consistency of C and Verilog using predicate abstraction and induction66-72 [doi]
- SAPOR: second-order Arnoldi method for passive order reduction of RCS circuitsYangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou. 74-79 [doi]
- SPRIM: structure-preserving reduced-order interconnect macromodelingRoland W. Freund. 80-87 [doi]
- Sparse and efficient reduced order modeling of linear subcircuits with large number of terminalsPeter Feldmann, F. Liu. 88-92 [doi]
- Fast simulation of VLSI interconnectsJitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan. 93-98 [doi]
- Cost-effective radiation hardening technique for combinational logicQuming Zhou, Kartik Mohanram. 100-106 [doi]
- Improving soft-error tolerance of FPGA configuration bitsSuresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin. 107-110 [doi]
- A soft error rate analysis (SERA) methodologyMing Zhang, Naresh R. Shanbhag. 111-118 [doi]
- Banked scratch-pad memory management for reducing leakage energy consumptionMahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, Ibrahim Kolcu. 120-124 [doi]
- Reducing cache misses by application-specific re-configurable indexingKimish Patel, Enrico Macii, Luca Benini, Massimo Poncino. 125-130 [doi]
- DynamoSim: a trace-based dynamically compiled instruction set simulatorMassimo Poncino, Jianwen Zhu. 131-136 [doi]
- The care and feeding of your statistical static timerSani R. Nassif, Duane S. Boning, Nagib Hakim. 138-139 [doi]
- Analytical modeling of crosstalk noise waveforms using Weibull functionAlireza Kasnavi, Joddy W. Wang, Mahmoud Shahram, Jindrich Zejda. 141-146 [doi]
- A robust cell-level crosstalk delay change analysisIgor Keller, Ken Tseng, Nishath K. Verghese. 147-154 [doi]
- Timing macro-modeling of IP blocks with crosstalkRuiming Chen, Hai Zhou. 155-159 [doi]
- Delay noise pessimism reduction by logic correlationsAlexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda. 160-167 [doi]
- Factoring and eliminating common subexpressions in polynomial expressionsAnup Hosangadi, Farzan Fallah, Ryan Kastner. 169-174 [doi]
- Custom-optimized multiplierless implementations of DSP algorithmsMarkus Püschel, Adam C. Zelinski, James C. Hoe. 175-182 [doi]
- A quantitative study and estimation models for extensible instructions in embedded processorsNewton Cheung, Sri Parameswaran, Jörg Henkel. 183-189 [doi]
- Code partitioning for synthesis of embedded applications with phantomAndré C. Nácul, Tony Givargis. 190-196 [doi]
- Formal verification coverage: computing the coverage gap between temporal specificationsSayantan Das, Prasenjit Basu, Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti, Chunduri Rama Mohan, Limor Fix, Roy Armoni. 198-203 [doi]
- Debugging sequential circuits using Boolean satisfiabilityMoayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir. 204-209 [doi]
- Towards formal verification of analog designsSmriti Gupta, Bruce H. Krogh, Rob A. Rutenbar. 210-217 [doi]
- Automatic translation of behavioral testbench for fully accelerated simulationYoung-Il Kim, Chong-Min Kyung. 218-221 [doi]
- Architectural-level synthesis of digital microfluidics-based biochipsFei Su, Krishnendu Chakrabarty. 223-228 [doi]
- Simultaneous design and placement of multiplexed chemical processing systems on microchipsAnton J. Pfeiffer, Tamal Mukherjee, Steinar Hauan. 229-236 [doi]
- A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologiesArijit Raychowdhury, Kaushik Roy. 237-240 [doi]
- Hybrid techniques for electrostatic analysis of nanowiresGang Li, Narayan R. Aluru. 241-244 [doi]
- Computation of signal threshold crossing times directly from higher order momentsYehea I. Ismail, Chirayu S. Amin. 246-253 [doi]
- Modeling unbuffered latches for timing analysisChirayu S. Amin, Florentin Dartu, Yehea I. Ismail. 254-260 [doi]
- A flexibility aware budgeting for hierarchical flow timing closureOlivier Omedes, Michel Robert, Mohammed Ramdani. 261-266 [doi]
- Energy optimization for a two-device data flow chainRavishankar Rao, Sarma B. K. Vrudhula. 268-274 [doi]
- A power aware system level interconnect design methodology for latency-insensitive systemsVikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi. 275-282 [doi]
- Exploiting level sensitive latches in wire pipeliningV. Seth, Min Zhao, Jiang Hu. 283-290 [doi]
- Floorplan design for multi-million gate FPGAsLei Cheng, Martin D. F. Wong. 292-299 [doi]
- Temporal floorplanning using the T-tree formulationPing-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang. 300-305 [doi]
- A thermal-driven floorplanning algorithm for 3D ICsJason Cong, Jie Wei, Yan Zhang. 306-313 [doi]
- A chip-level electrostatic discharge simulation strategyHaifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar. 315-318 [doi]
- Efficient full-chip thermal modeling and analysisPeng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra. 319-326 [doi]
- Interconnect lifetime prediction under dynamic stress for reliability-aware designZhijian Lu, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron. 327-334 [doi]
- Process and environmental variation impacts on ASIC timingPaul S. Zuchowski, Peter A. Habitz, J. D. Hayes, J. H. Oppold. 336-342 [doi]
- The impact of device parameter variations on the frequency and performance of VLSI chipsS. B. Samaan. 343-346 [doi]
- Variability in sub-100nm SRAM designsRaymond A. Heald, Ping Wang. 347-352 [doi]
- Application-specific buffer space allocation for networks-on-chip router designJingcao Hu, Radu Marculescu. 354-361 [doi]
- Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systemsAlexandru Andrei, Marcus T. Schmitz, Petru Eles, Zebo Peng, Bashir M. Al-Hashimi. 362-369 [doi]
- Hardware/software managed scratchpad memory for embedded systemAndhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic. 370-377 [doi]
- Physical placement driven by sequential timing analysisAaron P. Hurst, Philip Chong, Andreas Kuehlmann. 379-386 [doi]
- On interactions between routing and detailed placementDevang Jariwala, John Lillis. 387-393 [doi]
- Routability-driven placement and white space allocationChen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden. 394-401 [doi]
- True crosstalk aware incremental placement with noise mapHaoxing Ren, David Zhigang Pan, Paul Villarrubia. 402-409 [doi]
- On breakable cyclic definitionsJie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton. 411-418 [doi]
- Logical effort based technology mappingShrirang K. Karandikar, Sachin S. Sapatnekar. 419-422 [doi]
- Variability inspired implementation selection problemAzadeh Davoodi, Vishal Khandelwal, Ankur Srivastava. 423-427 [doi]
- M-trie: an efficient approach to on-chip logic minimizationSeraj Ahmad, Rabi N. Mahapatra. 428-435 [doi]
- Verifying properties of hardware and software by predicate abstraction and model checkingRandal E. Bryant, Sriram K. Rajamani. 437-438 [doi]
- Soft self-synchronising codes for self-calibrating communicationFrederic Worm, Paolo Ienne, Patrick Thiran. 440-447 [doi]
- SILENT: serialized low energy transmission coding for on-chip interconnection networksKangmin Lee, Se-Joong Lee, Hoi-Jun Yoo. 448-451 [doi]
- Optimal wire retiming without binary searchChuan Lin, Hai Zhou. 452-458 [doi]
- Interval-valued reduced order statistical interconnect modelingJames D. Ma, Rob A. Rutenbar. 460-467 [doi]
- Static statistical timing analysis for latch-based pipeline designsRob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu. 468-472 [doi]
- Efficient statistical timing analysis through error budgetingVishal Khandelwal, Azadeh Davoodi, Ankur Srivastava. 473-477 [doi]
- Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimatesNestoras E. Evmorfopoulos, Dimitris P. Karampatzakis, Georgios I. Stamoulis. 479-484 [doi]
- Fast flip-chip power grid analysis via locality and grid shellsEli Chiprout. 485-488 [doi]
- HiSIM: hierarchical interconnect-centric circuit simulatorTsung-Hao Chen, Jeng-Liang Tsai, Tanay Karnik. 489-496 [doi]
- Guiding CNF-SAT search via efficient constraint partitioningVijay Durairaj, Priyank Kalla. 498-501 [doi]
- Incremental deductive & inductive reasoning for SAT-based bounded model checkingLiang Zhang, Mukul R. Prasad, Michael S. Hsiao. 502-509 [doi]
- Efficient SAT-based unbounded symbolic model checking using circuit cofactoringMalay K. Ganai, Aarti Gupta, Pranav Ashar. 510-517 [doi]
- Efficient computation of small abstraction refinementsBing Li, Fabio Somenzi. 518-525 [doi]
- Exact and heuristic approaches to input vector control for leakage power reductionFeng Gao, John P. Hayes. 527-532 [doi]
- Leakage control through fine-grained placement and sizing of sleep transistorsVishal Khandelwal, Ankur Srivastava. 533-536 [doi]
- A vectorless estimation of maximum instantaneous current for sequential circuitsCheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang. 537-540 [doi]
- A new incremental placement algorithm and its application to congestion-aware divisor extractionSatrajit Chatterjee, Robert K. Brayton. 541-548 [doi]
- Unification of partitioning, placement and floorplanningSaurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov. 550-557 [doi]
- Multilevel expansion-based VLSI placement with blockagesBo Hu, Malgorzata Marek-Sadowska. 558-564 [doi]
- An analytic placer for mixed-size placement and timing-driven placementAndrew B. Kahng, Qinke Wang. 565-572 [doi]
- Engineering details of a stable force-directed placerKristofer Vorwerk, Andrew A. Kennings, Anthony Vannelli. 573-580 [doi]
- An integrated design flow for a via-configurable gate arrayYajun Ran, Malgorzata Marek-Sadowska. 582-589 [doi]
- A metal and via maskset programmable VLSI design methodology using PLAsNikhil Jayakumar, Sunil P. Khatri. 590-594 [doi]
- Analysis and evaluation of a hybrid interconnect structure for FPGAsRenqiu Huang, Ranga Vemuri. 595-601 [doi]
- Low-power programmable routing circuitry for FPGAsJason Helge Anderson, Farid N. Najm. 602-609 [doi]
- A yield improvement methodology using pre- and post-silicon statistical clock schedulingJeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja. 611-618 [doi]
- Clock schedule verification under process variationsRuiming Chen, Hai Zhou. 619-625 [doi]
- A novel clock distribution and dynamic de-skewing methodologyA. Kapoor, Nikhil Jayakumar, Sunil P. Khatri. 626-631 [doi]
- On per-test fault diagnosis using the X-fault modelXiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita. 633-640 [doi]
- Diagnosis of small-signal parameters for broadband amplifiers through S-parameter measurements and sensitivity-guided evolutionary searchFang Liu, Sule Ozev, Martin A. Brooke. 641-647 [doi]
- An efficient method for improving the quality of per-test fault diagnosisChunsheng Liu. 648-651 [doi]
- A unified theory of timing budget managementSoheil Ghiasi, Elaheh Bozorgzadeh, Siddharth Choudhuri, Majid Sarrafzadeh. 653-659 [doi]
- Dynamic range estimation for nonlinear systemsBin Wu, Jianwen Zhu, Farid N. Najm. 660-667 [doi]
- Power estimation for cycle-accurate functional descriptions of hardwareLin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 668-675 [doi]
- Efficient harmonic balance simulation using multi-level frequency decompositionPeng Li, Lawrence T. Pileggi. 677-682 [doi]
- Frequency domain simulation of high-Q oscillators with homotopy methodsXiaochun Duan, Kartikeya Mayaram. 683-686 [doi]
- Automated oscillator macromodelling techniques for capturing amplitude variations and injection lockingXiaolue Lai, Jaijeet S. Roychowdhury. 687-694 [doi]
- FLUTE: fast lookup table based wirelength estimation techniqueC. Chu. 696-701 [doi]
- Wire-length prediction using statistical techniquesJennifer L. Wong, Azadeh Davoodi, Vishal Khandelwal, Ankur Srivastava, Miodrag Potkonjak. 702-705 [doi]
- Accurate estimation of global buffer delay within a floorplanCharles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze. 706-711 [doi]
- A path-based methodology for post-silicon timing validationLeonard Lee, Li-C. Wang, T. M. Mak, Kwang-Ting Cheng. 713-720 [doi]
- Frugal linear network-based test decompression for drastic test cost reductionsWenjing Rao, Alex Orailoglu, G. Su. 721-725 [doi]
- Design space exploration for aggressive test cost reduction in CircularScan architecturesBaris Arslan, Alex Orailoglu. 726-731 [doi]
- Design/process learning from electrical testBernd Koenemann. 733-738 [doi]
- Backend CAD flows for restrictive design rules Mark A. Lavin, Fook-Luen Heng, Gregory A. Northrop. 739-746 [doi]
- Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depthMaxim Teslenko, Elena Dubrova. 748-751 [doi]
- DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designsDeming Chen, Jason Cong. 752-759 [doi]
- Vdd programmability to reduce FPGA interconnect powerFei Li, Yan Lin, Lei He. 760-765 [doi]
- Configuration bitstream compression for dynamically reconfigurable FPGAsLei He, Tulika Mitra, Weng-Fai Wong. 766-773 [doi]
- High-level synthesis: an essential ingredient for designing complex ASICsArvind, Rishiyur S. Nikhil, Daniel L. Rosenband, Nirav Dave. 775-782 [doi]
- High-level synthesis using computation-unit integrated memoriesChao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha. 783-790 [doi]
- Improved use of the carry-save representation for the synthesis of complex arithmetic circuitsAjay K. Verma, Paolo Ienne. 791-798 [doi]
- Formal derivation of optimal active shielding for low-power on-chip busesMaged Ghoneima, Yehea I. Ismail. 800-807 [doi]
- A general framework for probabilistic low-power design space exploration considering process variationAshish Srivastava, Dennis Sylvester. 808-813 [doi]
- Timing analysis considering spatial power/ground level variationMasanori Hashimoto, Junji Yamaguchi, Hidetoshi Onodera. 814-820 [doi]
- Simultaneous escape routing and layer assignment for dense PCBsMuhammet Mustafa Ozdal, Martin D. F. Wong. 822-829 [doi]
- A provably good algorithm for high performance bus routingMuhammet Mustafa Ozdal, Martin D. F. Wong. 830-837 [doi]
- Simultaneous short-path and long-path timing optimization for FPGAsRyan Fung, Vaughn Betz, William Chow. 838-845 [doi]
- Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizingGuido Stehr, Helmut E. Graeb, Kurt Antreich. 847-854 [doi]
- Robust analog/RF circuit design with projection-based posynomial modelingXin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi. 855-862 [doi]
- Techniques for improving the accuracy of geometric-programming based analog circuit design optimizationJintae Kim, Jaeseo Lee, Lieven Vandenberghe. 863-870 [doi]
- Variational interconnect analysis via PMTBRJoel R. Phillips. 872-879 [doi]
- Stochastic analysis of interconnect performance in the presence of process variationsJanet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula. 880-886 [doi]
- A stochastic integral equation method for modeling the rough surface effect on interconnect capacitanceZhenhai Zhu, Jacob White, Alper Demir. 887-891 [doi]
- Detection of multiple transitions in delay fault test of SPARC64 microprocessorDaisuke Maruyama, Akira Kanuma, Takashi Mochiyama, Hiroaki Komatsu, Yaroku Sugiyama, Noriyuki Ito. 893-898 [doi]
- Minimizing the number of test configurations for FPGAsErik Chmelar. 899-902 [doi]
- SPIN-TEST: automatic test pattern generation for speed-independent circuitsFeng Shi, Yiorgos Makris. 903-908 [doi]
- How to bridge the abstraction gap in system level modeling and designA. Bernstein, M. Burton, Frank Ghenassia. 910-914 [doi]
- Analyzing software influences on substrate noise: an ADC perspectiveFrank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin. 916-922 [doi]
- Design space exploration for a UMTS front-end exploiting analog platformsF. De Bernarclinis, S. Gambini, R. Vincis, F. Svelto. 923-930 [doi]
- Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splinesRanga Vemuri, Glenn Wolfe. 931-938 [doi]