Abstract is missing.
- Statistical generalization: theory and applicationsBenjamin W. Wah, Arthur Ieumwananonthachai, Shu Yao, Ting Yu. 4 [doi]
- Signal propagation in high-speed MCM circuitsC. Truzzi, Eric Beyne, E. Ringoot, J. Peeters. 12-17 [doi]
- Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodelJimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai. 18-24 [doi]
- A CMOS gate array with dynamic-termination GTL I/O circuitsJunya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito. 25 [doi]
- Precise exception handling for a self-timed processorWilliam F. Richardson, Erik Brunvand. 32-37 [doi]
- Implementing a STARI chipMark R. Greenstreet. 38-43 [doi]
- A high-performance asynchronous SCSI controllerKenneth Y. Yun, David L. Dill. 44 [doi]
- Performance assessment of embedded Hw/Sw systemsJean Paul Calvez, Olivier Pasquier. 52-57 [doi]
- Performance estimation for real-time distributed embedded systemsTi-Yen Yen, Wayne Wolf. 64-71 [doi]
- Verifying the performance of the PCI local bus using symbolic techniquesSérgio Vale Aguiar Campos, Edmund M. Clarke, Wilfredo R. Marrero, Marius Minea. 72-78 [doi]
- Extending VLSI design with higher-order logicAnand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu. 85 [doi]
- Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessorSteven Wallace, Nirav Dagli, Nader Bagherzadeh. 96-101 [doi]
- A superscalar RISC processor with pseudo vector processing featureKotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa. 102-109 [doi]
- The resource conflict methodology for early-stage design space exploration of superscalar RISC processorsJohn-David Wellman, Edward S. Davidson. 110 [doi]
- Design of an efficient power distribution network for the UltraSPARC-I microprocessorAlexander Dalal, Lavi Lev, Sundari Mitra. 118-123 [doi]
- Clock controller design in SuperSPARC II microprocessorH. Hao, K. Bhabuthmal. 124-129 [doi]
- Incas: a cycle accurate model of UltraSPARCGuillermo Maturana, James L. Ball, Jeffery Gee, Amaresh Iyer, J. Michael O Connor. 130-137 [doi]
- Accurate device modeling techniques for efficient timing simulation of integrated circuitsAnirudh Devgan. 138-143 [doi]
- Execution-time profiling for multiple-process behavioral synthesisJay K. Adams, John Alan Miller, Donald E. Thomas. 144-149 [doi]
- Emulation verification of the Motorola 68060Jainendra Kumar, Noel R. Strader, Jeff Freeman, Michael Miller. 150 [doi]
- Testability analysis and insertion for RTL circuits based on pseudorandom BISTJoan Carletta, Christos A. Papachristou. 162-167 [doi]
- Efficient testability enhancement for combinational circuitYu Fang, Alexander Albicki. 168-179 [doi]
- Design for hierarchical testability of RTL circuits obtained by behavioral synthesisIndradeep Ghosh, Anand Raghunathan, Niraj K. Jha. 173-179 [doi]
- Synthesis for testability of large complexity controllersFranco Fummi, Donatella Sciuto, M. Serro. 180 [doi]
- The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessorCarlos Montemayor, Marie Sullivan, Jen-Tien Yen, Pete Wilson, Richard Evers, K. R. Kishore. 196-203 [doi]
- A high performance bus and cache controller for PowerPC multiprocessing systemsMichael S. Allen, W. Kurt Lewchuk, J. D. Coddington. 204-211 [doi]
- Performance monitoring on the PowerPC 604 microprocessorCharles P. Roth, Frank E. Levine, Edward H. Welbon. 212 [doi]
- Thermal placement for high-performance multichip modulesKai-Yuan Chao, D. F. Wong. 218-223 [doi]
- EPNR: an energy-efficient automated layout synthesis packageGlenn Holt, Akhilesh Tyagi. 224-229 [doi]
- PEPPER - a timing driven early floorplannerVinod Narayananan, David LaPotin, Rajesh K. Gupta, Gopalakrishnan Vijayan. 230-235 [doi]
- Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioningJin-Tai Yan. 236 [doi]
- An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functionsTomasz Kozlowski, Erik L. Dagless, Jonathan Saul. 244-249 [doi]
- Implicit state minimization of non-deterministic FSMsTimothy Kam, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 250-257 [doi]
- Adaptive routing in Clos networksPeter A. Franaszek, Christos J. Georgiou, Chung-Sheng Li. 266-270 [doi]
- Rational clocking [digital systems design]Luis F. G. Sarmenta, Gill A. Pratt, Stephen A. Ward. 271-278 [doi]
- A prototype router for the massively parallel computer RWC-1T. Yokota, H. Matsuoka, K. Okamoto, H. Hirono, A. Hori, S. Sakai. 279 [doi]
- Concurrent automatic test pattern generation algorithm for combinational circuitsAbdel-Fattah Yousif, Jun Gu. 286-291 [doi]
- Test generation for multiple state-table faults in finite-state machinesIrith Pomeranz, Sudhakar M. Reddy. 292 [doi]
- Pollution control cachingStephen J. Walsh, John A. Board. 300 [doi]
- Caching processor general registersRobert Yung, Neil C. Wilhelm. 307-312 [doi]
- A dynamic cache sub-block design to reduce false sharingMurali Kadiyala, Laxmi N. Bhuyan. 313 [doi]
- A programmable routing controller for flexible communications in point-to-point networksStuart W. Daniel, Jennifer Rexford, James W. Dolter, Kang G. Shin. 320-331 [doi]
- POM: a processor model for image processingJean-Paul Theis, Lothar Thiele. 326-331 [doi]
- A case study in low-power system-level designAndrew Wolfe. 332 [doi]
- A novel architecture for an ATM switchJin Li, Chuan-lin Wu. 340-345 [doi]
- Architecture and design of a 40 gigabit per second ATM switchSteven E. Butner, David A. Skirmont. 352 [doi]
- Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuitsFrederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs. 360-365 [doi]
- An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing orderingJin-Tai Yan. 366-371 [doi]
- FPGA global routing based on a new congestion metricYao-Wen Chang, D. F. Wong, C. K. Wong. 372 [doi]
- Asynchronous 2-D discrete cosine transform core processorBret Stott, Dave Johnson, Venkatesh Akella. 380-385 [doi]
- A self-timed redundant-binary number to binary number converter for digital arithmetic processorsChin-Long Wey, Haiyan Wang, Cheng-Ping Wang. 386 [doi]
- Design and analysis of FPGA/FPIC switch modulesYao-Wen Chang, D. F. Wong, C. K. Wong. 394-401 [doi]
- Simultaneous area and delay minimum K-LUT mapping for K-exact networksShashidhar Thakur, D. F. Wong. 402-408 [doi]
- DART: delay and routability driven technology mapping for LUT based FPGAsAigo Lu, Erik L. Dagless, Jonathan M. Saul. 409-414 [doi]
- Logic synthesis for a single large look-up tableRajeev Murgai, Masahiro Fujita, Fumiyasu Hirose. 415 [doi]
- Testing-what s missing? An incomplete list of challengesSudhakar M. Reddy. 426 [doi]
- Analysis of conditional resource sharing using a guard-based control representationIvan P. Radivojevic, Forrest Brewer. 434-445 [doi]
- Multi-dimensional interleaving for time-and-memory design optimizationNelson L. Passos, Edwin Hsing-Mean Sha, Liang-Fang Chao. 440-445 [doi]
- High level profiling based low power synthesis techniqueSrinivas Katkoori, Nand Kumar, Ranga Vemuri. 446 [doi]
- Control unit synthesis targeting low-power processorsChuan-Yu Wang, Kaushik Roy. 454 [doi]
- Low power data format converter design using semi-static register allocationKala Srivatsan, Chaitali Chakrabarti, Lori Lucke. 460-465 [doi]
- A 13.3ns double-precision floating-point ALU and multiplierH. Yamada, T. Hotta, T. Nishiyama, F. Murabayashi, T. Yamauchi, H. Sawamoto. 466 [doi]
- A floating point radix 2 shared division/square root chipHosahalli R. Srinivas, Keshab K. Parhi. 472-478 [doi]
- High-radix SRT division with speculation of quotient digits Tzu-Hsi Pan, Hyon-Sok Kay, Youngsun Chun, Chin-Long Wey. 479 [doi]
- Special purpose FPGA for high-speed digital telecommunication systemsAkihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta. 486-491 [doi]
- VLSI design of densely-connected array processorsEric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang. 492-497 [doi]
- VLSI issues in memory-system design for video signal processorsSantanu Dutta, Wayne Wolf, Andrew Wolfe. 498 [doi]
- Write buffer design for cache-coherent shared-memory multiprocessorsFarnaz Mounes-Toussi, David J. Lilja. 506-511 [doi]
- Reducing data access penalty using intelligent opcode-driven cache prefetchingChi-Hung Chi, Siu-Chung Lau. 512-517 [doi]
- Interrupt-based hardware support for profiling memory system performanceAaron Goldberg, John A. Trotter. 518 [doi]
- Verification of a subtractive radix-2 square root algorithm and implementationMiriam Leeser, John W. O Leary. 526-531 [doi]
- Automatic extraction of the control flow machine and application to evaluating coverage of verification vectorsYatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham. 532-537 [doi]
- Theorem proving: not an esoteric diversion, but the unifying framework for industrial verificationDavid Cyrluk, Mandayam K. Srivas. 538 [doi]
- An empirical study of datapath, memory hierarchy, and network in SIMD array architecturesMartin C. Herbordt, Charles C. Weems. 546-551 [doi]
- Memory organization for video algorithms on programmable signal processorsEddy de Greef, Francky Catthoor, Hugo De Man. 552-557 [doi]
- SSM-MP: more scalability in shared-memory multi-processorShigeaki Iwasa, Shung Ho Shing, Hisashi Mogi, Hiroshi Nozuwe, Hiroo Hayashi, Osamu Wakamori, Takashi Ohmizo, Kuninori Tanaka, Hiroshi Sakai, Mitsuo Saito. 558 [doi]
- Low power and high speed multiplication design through mixed number representationsMenghui Zheng, Alexander Albicki. 566-576 [doi]
- Estimation of sequential circuit activity considering spatial and temporal correlationsTan-Li Chou, Kaushik Roy. 577 [doi]
- A symbolic-simulation approach to the timing verification of interacting FSMsAjay J. Daga, William P. Birmingham. 584-589 [doi]
- Incremental methods for FSM traversalGitanjali Swamy, Robert K. Brayton, Vigyan Singhal. 590 [doi]
- Extraction of finite state machines from transistor netlists by symbolic simulationManish Pandey, Alok Jain, Randal E. Bryant, Derek L. Beatty, Gary York, Samir Jain. 596-601 [doi]
- Dynamic minimization of OKFDDsRolf Drechsler, Bernd Becker. 602 [doi]
- Data parallel fault simulationMinesh B. Amin, Bapiraju Vinnakota. 610-615 [doi]
- A parallel algorithm for fault simulation based on PROOFS Steven Parkes, Prithviraj Banerjee, Janak H. Patel. 616 [doi]
- Statistics on concurrent fault and design error simulationBrian Grayson, Saghir A. Shaikh, Stephen A. Szygenda. 622-627 [doi]
- A new architectural-level fault simulation using propagation prediction of grouped fault-effectsMichael S. Hsiao, Janak H. Patel. 628 [doi]
- A CMOS wave-pipelined image processor for real-time morphology Ram K. Krishnamurthy, Ramalingam Sridhar. 638 [doi]
- An efficient systolic array for the discrete cosine transform based on prime-factor decomposition Hyesook Lim, Earl E. Swartzlander Jr.. 644-649 [doi]
- Systolic algorithms for tree pattern matchingAbdel Ejnioui, N. Ranganathan. 650-702 [doi]
- Logic extraction based on normalized netlengthsHirendu Vaishnav, Massoud Pedram. 658-663 [doi]
- Transformation of min-max optimization to least-square estimation and application to interconnect design optimizationJimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai. 664-670 [doi]
- Simple tree-construction heuristics for the fanout problem Robert J. Carragher, Masahiro Fujita, Chung-Kuan Cheng. 671-679 [doi]
- Concurrent timing optimization of latch-based digital systemsHong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray. 680 [doi]
- A coprocessor for accurate and reliable numerical computationsMichael J. Schulte, Earl E. Swartzlander Jr.. 686 [doi]
- Efficient state assignment framework for asynchronous state graphsChantal Ykman-Couvreur, Bill Lin. 692 [doi]
- Distributed automatic test pattern generation with a parallel FAN algorithmStefan Radtke, Jens Bargfrede, Walter Anheier. 698 [doi]
- Smart-pixel array processors based on optimal cellular neural networks for space sensor applicationsWai-Chi Fang, Bing J. Sheu, Holger Venus, Rainer Sandau. 703 [doi]