Table of Contents

• Testing silicon TV tuners on ATE without TV signal generatorY. Fan, A. Verma, J. Janney, S. Kumar. 1-9 [doi]
• Comparing the effectiveness of cache-resident tests against cycleaccurate deterministic functional patternsSankar Gurumurthy, Mustansir Pratapgarhwala, Curtis Gilgan, Jeff Rearick. 1-8 [doi]
• The case for analyzing system level failures using structural patternsHarry H. Chen. 1 [doi]
• Clustering-based failure triage for RTL regression debuggingZissis Poulos, Andreas G. Veneris. 1-10 [doi]
• IC laser trimming speed-up through wafer-level spatial correlation modelingConstantinos Xanthopoulos, Ke Huang, Abbas Poonawala, Amit Nahar, Bob Orr, John M. Carulli Jr., Yiorgos Makris. 1-7 [doi]
• Delivering security by design in the Internet of ThingsBill Curtis. 1 [doi]
• FAST-BIST: Faster-than-at-Speed BIST targeting hidden delay defectsSybille Hellebrand, Thomas Indlekofer, Matthias Kampmann, Michael A. Kochte, Chang Liu, Hans-Joachim Wunderlich. 1-8 [doi]
• Counterfeit IC detection using light emissionPeilin Song, Franco Stellari, Alan J. Weger. 1-8 [doi]
• A test probe for TSV using resonant inductive couplingRashid Rashidzadeh, Iftekhar Ibne Basith. 1-10 [doi]
• Recruiting distributed resources for grid resilience: The need for transparencyAlexandra von Meier. 1 [doi]
• Challenges of testing 100M chipsSajjad Pagarkar. 1 [doi]
• Protecting against emerging vmin failures in advanced technology nodesJ. K. Jerry Lee, Amr Haggag, William Eklow. 1-7 [doi]
• Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modelingShanghang Zhang, Xin Li, R. D. Blanton, José Machado da Silva, John M. Carulli Jr., Kenneth M. Butler. 1-10 [doi]
• Isometric test compression with low toggling activityA. Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang. 1-7 [doi]
• Welcome messageMichael Purtell, Subhasish Mitra. 1-2 [doi]
• Microgrids as a resiliency resourceKevin Schneider. 1 [doi]
• Market opportunities and testing challenges for millimeter-wave radios and radarsBrian A. Floyd. 1 [doi]
• Robustness of TAP-based scan networksFarrokh Ghani Zadegan, Gunnar Carlsson, Erik Larsson. 1-10 [doi]
• Emulation and its connection to testKenneth Larsen. 1 [doi]
• Redundancy architectures for channel-based 3D DRAM yield improvementBing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang. 1-7 [doi]
• Practical random sampling of potential defects for analog fault simulationStephen Sunter, Krzysztof Jurga, Peter Dingenen, Ronny Vanhooren. 1-10 [doi]
• Board manufacturing test correlation to IC manufacturing testC. Glenn Shirley, W. Robert Daasch, Phil Nigh, Zoe Conroy. 1-8 [doi]
• On-chip constrained random stimuli generation for post-silicon validation using compact masksXiaobing Shi, Nicola Nicolici. 1-10 [doi]
• Software in a hardware view: New models for HW-dependent software in SoC verification and testCarlos Villarraga, Bernard Schmidt, Binghao Bao, Rakesh Raman, Christian Bartsch, Thomas Fehmel, Dominik Stoffel, Wolfgang Kunz. 1-9 [doi]
• Wafer Level Chip Scale Package copper pillar probingHao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang. 1-6 [doi]
• Read disturb fault detection in STT-MRAMRajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori. 1-7 [doi]
• Top ten challenges in Big Data security and privacyPraveen K. Murthy. 1 [doi]
• Fast BIST of I/O Pin AC specifications and inter-chip delaysStephen Sunter, Saghir A. Shaikh, Qing Lin. 1-8 [doi]
• Feature engineering with canonical analysis for effective statistical tests screening test escapesFan Lin, Chun-Kai Hsu, Kwang-Ting Cheng. 1-10 [doi]
• Teaching an old dog new tricks: Views on the future of mixed-signal IC designBoris Murmann. 1 [doi]
• Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiationChen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam. 1-6 [doi]
• Mitigating voltage droop during scan with variable shift frequencyJohn Schulze, Ryan Tally. 1-8 [doi]
• Thermal-aware mobile SoC design and test in 14nm finfet technologyBong Hyun Lee. 1 [doi]
• Big data and testAnne Gattiker. 1 [doi]
• The desire-friction ratio of Adaptive testStacy Ajouri. 1 [doi]
• A distributed, reconfigurable, and reusable bist infrastructure for 3D-stacked ICsMukesh Agrawal, Krishnendu Chakrabarty, Bill Eklow. 1-10 [doi]
• A tale of two lives: Under test and in the wildBianca Schroeder. 1 [doi]
• Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAsLuca Cassano. 1-10 [doi]
• Low-distortion signal generation for ADC testingFumitaka Abe, Yutaro Kobayashi, Kenji Sawada, Keisuke Kato, Osamu Kobayashi, Haruo Kobayashi. 1-10 [doi]
• Managing signal, power and thermal integrity for 3D integrationMadhavan Swaminathan. 1 [doi]
• An efficient diagnosis-aware pattern generation procedure for transition faultsKuen-Jong Lee, Cheng-Hung Wu. 1-10 [doi]
• Compositional verification using formal analysis for a flight critical systemGuillaume Brat. 1 [doi]
• Test-mode-only scan attack and countermeasure for contemporary scan architecturesSamah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, Ramesh Karri. 1-8 [doi]
• On the testing of hazard activated open defectsChao Han, Adit D. Singh. 1-6 [doi]
• EAGLE: A regression model for fault coverage estimation using a simulation based metricShahrzad Mirkhani, Jacob A. Abraham. 1-10 [doi]
• Knowledge discovery and knowledge transfer in board-level functional fault diagnosisFangming Ye, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
• A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test timeBruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang. 1-10 [doi]
• A Tag based solution for efficient utilization of efuse for memory repairHarsharaj Ellur, Kalpesh Shah. 1-7 [doi]
• Systematic approach for trim test time optimization: Case study on a multi-core RF SOCRajesh Mittal, Mudasir Kawoosa, Rubin A. Parekhji. 1-9 [doi]
• Analytical MRAM testRaphael Robertazzi, Janusz Nowak, Jonathan Sun. 1-10 [doi]
• Design, test & repair methodology for FinFET-based memoriesYervant Zorian. 1 [doi]
• Error prediction and detection methodologies for reliable circuit operation under NBTIJulio Vazquez Hernandez. 1-10 [doi]
• Board security enhancement using new locking SIB-based architecturesJennifer Dworak, Zoe Conroy, Alfred L. Crouch, John C. Potter. 1-10 [doi]
• Low-cost phase noise testing of complex RF ICs using standard digital ATEStephane David-Grignot, Florence Azaïs, Laurent Latorre, Francois Lefevre. 1-9 [doi]
• Test pattern generation in presence of unknown values based on restricted symbolic logicDominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker. 1-10 [doi]
• Massive signal tracing using on-chip DRAM for in-system silicon debugSergej Deutsch, Krishnendu Chakrabarty. 1-10 [doi]
• Intra-die process variation aware anomaly detection in FPGAsYoungok Pino, Vinayaka Jyothi, Matthew French. 1-6 [doi]
• Yield optimization using advanced statistical correlation methodsJeff Tikkanen, Sebastian Siatkowski, Nik Sumikawa, Li-C. Wang, Magdy S. Abadir. 1-10 [doi]
• Logic characterization vehicle design for maximal information extraction for yield learningR. D. Blanton, Ben Niewenhuis, Carl Taylor. 1-10 [doi]
• Collaboration and teamwork obstaclesWesley Smith. 1 [doi]
• Design, technology and yield in the post-moore eraGreg Yeric. 1 [doi]
• Optimizing redundancy design for chip-multiprocessors for flexible utility functionsDa Cheng, Sandeep K. Gupta. 1-8 [doi]
• Low cost back end signal processing driven bandwidth interleaved signal acquisition using free running undersampling clocks and mixing signalsNicholas Tzou, Debesh Bhatta, Abhijit Chatterjee. 1-10 [doi]
• Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screeningAndreas Kux, Rudolf Ullmann, Thomas Kern, Roland Strunz, Hanno Melzner, Stephan Beuven, Andreas Haase. 1-7 [doi]
• At-speed capture power reduction using layout-aware granular clock gate enable controlsR. Shaikh, P. Wilson, K. Agarwal, H. V. Sanjay, R. Tiwari, K. Lath, S. Ravi. 1-10 [doi]
• Divide and conquer diagnosis for multiple defectsShih-Min Chao, Po-Juei Chen, Jing-yu Chen, Po-Hao Chen, Ang-Feng Lin, James Chien-Mo Li, Pei-Ying Hsueh, Chun-Yi Kuo, Ying-Yen Chen, Jih-Nung Li. 1-8 [doi]
• Fault sharing in a copy-on-write based ATPG systemX. Cai, Peter Wohl, D. Martin. 1-8 [doi]
• Analog fault models: Back to the future?Mani Soma. 1 [doi]
• Efficient testing of hierarchical core-based SOCsBrion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen. 1-10 [doi]
• ATE and test equipment vendors; Hardware not softwareMark Roos. 1 [doi]
• Dynamic microgrids - A potential solution for enhanced resiliency in distribution systemsMani Vadari. 1 [doi]
• Yield and performance improvement through technology-design co-optimization in advanced technology nodesYue Liang. 1 [doi]
• Interposer test: Testing PCBs that have shrunk 100xT. M. Mak. 1 [doi]
• A diagnosis-friendly LBIST architecture with property checkingSarvesh Prabhu, Vineeth V. Acharya, Sharad Bagri, Michael S. Hsiao. 1-9 [doi]
• Fast co-test of linearity and spectral performance with non-coherent sampled and amplitude clipped dataLi Xu, Degang Chen. 1-8 [doi]
• Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkillsMasahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada. 1-10 [doi]
• Improving test compression with scan feedforward techniquesSreenivaas S. Muthyala, Nur A. Touba. 1-10 [doi]
• DfST: Design for secure testabilitySamah Mohamed Saeed. 1-10 [doi]
• A built-in self-test circuit for jitter tolerance measurement in high-speed wireline receiversMyeong-Jae Park, Jaeha Kim. 1-6 [doi]
• The importance of DFX, a foundry perspectiveSaman Adham, Jonathan Chang, Hung-Jen Liao, John Hung, Ting-Hua Hsieh. 1-6 [doi]
• Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interfaceErik Jan Marinissen, Bart De Wachter, Ken Smith, Jorg Kiesewetter, Mottaqiallah Taouil, Said Hamdioui. 1-10 [doi]
• Efficient SAT-based ATPG techniques for all multiple stuck-at faultsMasahiro Fujita, Alan Mishchenko. 1-10 [doi]
• Vesuvius-3D: A 3D-DfT demonstratorErik Jan Marinissen, Bart De Wachter, Stephen O'Loughlin, Sergej Deutsch, Christos Papameletis, Tobias Burgherr. 1-10 [doi]
• Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processorsKeith A. Bowman, Alex Park, Venkat Narayanan, Francois Atallah, Alain Artieri, Sei Seung Yoon, Kendrick Yuen, David Hansquine. 1 [doi]
• Process defect trends and strategic test gapsPaul G. Ryan, Irfan Aziz, William B. Howell, Teresa K. Janczak, Davia J. Lu. 1-8 [doi]
• Efficient RAS support for die-stacked DRAMHyeran Jeon, Gabriel H. Loh, Murali Annavaram. 1-10 [doi]
• Concerns over predictability of supply and qualityCarl Bowen. 1 [doi]
• Security solutions in the first-generation Zynq All-Programmable SoCSteve Trimberger. 1 [doi]
• A novel RF self test for a combo SoC on digital ATE with multi-site applicationsChun-Hsien Peng, ChiaYu Yang, Adonis Tsu, Chung-Jin Tsai, Yosen Chen, C. Y. Lin, Kai Hong, Kaipon Kao, Paul C. P. Liang, Chao Long Tsai, Charles Chien, H. C. Hwang. 1-8 [doi]
• A self-tuning architecture for buck converters based on alternative testXian Wang, Blanchard Kenfack, Estella Silva, Abhijit Chatterjee. 1-10 [doi]
• Achieving extreme scan compression for SoC DesignsPeter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane. 1-8 [doi]
• Design and test of analog circuits towards sub-ppm levelGeorges Gielen, Wim Dobbelaere, Ronny Vanhooren, Anthony Coyette, Baris Esen. 1-2 [doi]
• Energy-secure computer architecturesPradip Bose. 1 [doi]
• Spatio-temporal wafer-level correlation modeling with progressive sampling: A pathway to HVM yield estimationAli Ahmadi, Ke Huang, Suriyaprakash Natarajan, John M. Carulli Jr., Yiorgos Makris. 1-10 [doi]