IEEE Design & Test of Computers - researchr journal

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2	--	3	. What s Ahead for 1991?
5	--	0	. D&T News
8	--	23	Nikil D. Dutt, Daniel D. Gajski. Design Synthesis and Silicon Compilation
24	--	40	Jung-Gen Wu, Yu Hen Hu, William P.-C. Ho, David Y. Y. Yun. A Model-Based Expert System for Digital System Design
42	--	49	Peter M. Maurer. Dynamic Functional Testing for VLSI Circuits
50	--	59	. A D&T Roundtable: Synthesis for Testability
60	--	65	. 1990 Annual Index
70	--	71	. TTTC Newsletter

3	--	4	. D&T News
6	--	7	Giovanni De Micheli. Guest Editorial: High-Level Synthesis of Digital Circuits
8	--	19	Raul Camposano. From Behavior to Structure: High-Level Synthesis
20	--	36	Jayaram Bhasker, Huan-Chih Lee. An Optimizer for Hardware Synthesis
37	--	53	Giovanni De Micheli, David C. Ku, Frederic Mailhot, Thomas K. Truong. The Olympus Synthesis System
54	--	57	Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong. Neural Net and Boolean Satisfiability Models of Logic Circuits
62	--	63	. DATC Newsletter

2	--	0	. D&T News
4	--	0	Kenneth D. Wagner. Guest Editorial: The Many Faces of Test
5	--	12	Sandip Kundu, Sudhakar M. Reddy. Embedded Totally Self-Checking Checkers: A Practical Design
13	--	25	David A. Wood, Garth A. Gibson, Randy H. Katz. Verifying a Multiprocessor Cache Controller Using Random Test Generation
26	--	31	Kewal K. Saluja, Kyuchull Kim. Improved Test Generation for High-Activity Circuits
32	--	35	Vishwani D. Agrawal, Hatsuyoshi Kato. Fault Sampling Revisited
36	--	38	A. Ahmad, N. K. Nanda, K. Garg. Are Primitive Polynomials Always Best in Signature Analysis?
39	--	51	Sakti P. Ghosh, Edward G. Grochowski. Dynamic Statistical Control of Manufacturing Test
52	--	65	Jer Min Jou, Jau-Yien Lee, Yachyang Sun, Jhing-Fa Wang. An Efficient VLSI Switch-Box Router
66	--	72	. A D&T Roundtable: System Test-What, Why, and How?
78	--	79	. TTTC Newsletter

0	--	0	. D&T News
8	--	10	James R. Armstrong. Tuning VHDL for Multivalve Logic Modeling
12	--	23	Paul J. Menchini. A Minimalist Approach to VHDL Logic Modeling
25	--	32	David R. Coelho. A VHDL Standard Package for Logic Modeling
33	--	41	Steven P. Smith, Ramón D. Acosta. A Value System for Switch-Level Modeling
42	--	48	Joanne DeGroat. Transparent Logic Modeling in VHDL
49	--	55	Alfred S. Gilman. Logic Modeling in WAVES
56	--	63	. A D&T Roundtable: Does VLSI Education Meet Industry s Needs?
70	--	71	. DATC Newsletter

2	--	3	M. Ray Mercer. Guest Editorial: ITC 20th Anniversary
4	--	14	Christopher W. Branson. Integrating Tester Pin Electronics
15	--	28	Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater. Low-Cost Testing of High-Density Logic Components
29	--	40	Richard Illman, Stephen Clarke. Built-In Self-Test of the Macrolan Chip
41	--	51	Frans P. M. Beenker, Barry J. Dekker, Richard Stans, Max Van der Star. Implementing Macro Test in Silicon Compiler Design
52	--	63	Benoit Nadeau-Dostie, Allan Silburt, Vinod K. Agarwal. Serial Interfacing for Embedded-Memory Testing

0	--	0	. D&T News
4	--	0	. Editorial Calendar
6	--	8	Ben Bennetts. Test Technology in Europe
9	--	19	R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg. Designing and Implementing an Architecture with Boundary Scan
20	--	25	Hugu K. Seitz, Armin Blacha, Rolf Clauberg, H. Beha, J. Feder. Contactless High-Speed Waveform Measurements on Gallium
26	--	38	Phil Nigh, Wojciech Maly. Test Generation for Current Testing (CMOS ICs)
39	--	45	Bas Verhelst. Using a Test-Specification Format in Automatic Test-Program Generation
46	--	54	. The Challenges of Self-Test
56	--	62	. A D&T Roundtable: Behavioral Description Languages, Part 1: Are Designers Benefitting?
63	--	67	. The 1989 Annual Index
70	--	71	. DATC Newsletter

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