| 398 | -- | 407 | Raghu Sastry, N. Ranganathan, Horst Bunke. VLSI architectures for polygon recognition |
| 408 | -- | 414 | Anna Antola, Alberto Avai, Luca Breveglieri. Modular design methodologies for image processing architectures |
| 415 | -- | 422 | Dinesh Somasekhar, V. Visvanathan. A 230-MHz half-bit level pipelined multiplier using true single-phase clocking |
| 423 | -- | 431 | Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d Abreu. Greedy hardware optimization for linear digital circuits using number splitting and refactorization |
| 432 | -- | 440 | Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. ESPRESSO-SIGNATURE: a new exact minimizer for logic functions |
| 441 | -- | 445 | Vinaya Kumar Singh, A. A. Diwan. A heuristic for decomposition in multilevel logic optimization |
| 446 | -- | 452 | W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana. Faulty behavior of storage elements and its effects on sequential circuits |
| 453 | -- | 461 | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal. Path delay fault simulation of sequential circuits |
| 462 | -- | 472 | Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani. Middle terminal cell models for efficient over-the-cell routing in high-performance circuits |
| 473 | -- | 481 | Ed P. Huijbregts, Jochen A. G. Jess. General gate array routing using a k-terminal net routing algorithm with failure prediction |
| 482 | -- | 490 | K. S. V. Gopalarao, Purnendu K. Mozumder, Duane S. Boning. An integrated technology CAD system for process and device designers |
| 491 | -- | 502 | Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W. L. Yang. The design and implementation of the Arithmetic Cube II, a VLSI signal processing system |
| 503 | -- | 513 | Kaushik Roy, S. C. Prasad. Circuit activity based logic synthesis for low power reliable operations |
| 514 | -- | 525 | K. De, P. Banerjee. PREST: a system for logic partitioning and resynthesis for testability |
| 526 | -- | 536 | Dimitrios Kagaris, Spyros Tragoudas. Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets |
| 537 | -- | 545 | D. Das, Sharad C. Seth, Vishwani D. Agrawal. Accurate computation of field reject ratio based on fault latency |
| 546 | -- | 558 | D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan. Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model |
| 559 | -- | 562 | David C. Blight, Robert D. McLeod. An adaptive message passing environment for water scale systems |
| 562 | -- | 566 | R. Varadarajan, F. Augustine. Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme |
| 566 | -- | 571 | C. Bachelu, Martin Lefebvre. A study of the use of local interconnect in CMOS leaf cell design |
| 571 | -- | 575 | C. Ying, J. Gu. Automated pin grid array package routing on multilayer ceramic substrates |