| 469 | -- | 471 | Allen C.-H. Wu, Nikil D. Dutt. Guest editorial 11th international symposium on system-level synthesis and design (ISSS 98) |
| 472 | -- | 491 | Petru Eles, Alex Doboli, Paul Pop, Zebo Peng. Scheduling with bus access optimization for distributed embedded systems |
| 492 | -- | 502 | Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha. Performance improvement of geographically distributed cosimulation by hierarchically grouped messages |
| 503 | -- | 516 | Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu. Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core |
| 517 | -- | 521 | Ying Zhao, Sharad Malik. Exact memory size estimation for array computations |
| 522 | -- | 526 | Wonyong Sung, Soonhoi Ha. Memory efficient software synthesis with mixed coding style from dataflow graphs |
| 526 | -- | 530 | Dominique Borrione, Julia Dushina, Laurence V. Pierre. A compositional model for the functional verification of high-level synthesis results |
| 530 | -- | 533 | Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo, Ricardo Pannain. Expression-tree-based algorithms for code compression on embedded RISC architectures |
| 534 | -- | 541 | Bassam Shaer, Sami A. Al-Arian, David L. Landis. Partitioning sequential circuits for pseudoexhaustive testing |
| 542 | -- | 557 | Montek Singh, Steven M. Nowick. Synthesis for logical initializability of synchronous finite-state machines |
| 558 | -- | 572 | Christian Pacha, U. Auer, C. Burwick, Peter Glösekötter, A. Brennemann, W. Prost, F.-J. Tegude, K. F. Goser. Threshold logic circuit design of parallel adders using resonant tunneling devices |
| 573 | -- | 583 | Allen E. Sjogren, Chris J. Myers. Interfacing synchronous and asynchronous modules within a high-speed pipeline |
| 584 | -- | 593 | Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram. Improving the efficiency of Monte Carlo power estimation [VLSI] |
| 594 | -- | 605 | Han Bin Kim, Dong Sam Ha, Takeshi Takahashi, Takahiro J. Yamaguchi. A new approach to built-in self-testable datapath synthesis based on integer linear programming |
| 606 | -- | 609 | F. Caignet, S. D.-B. Dhia, E. Sicard. On the measurement of crosstalk in integrated circuits |
| 610 | -- | 614 | Ananta K. Majhi, V. D. Agrawak, James Jacob, Lalit M. Patnaik. Line coverage of path delay faults |
| 614 | -- | 624 | Pasquale Corsonello, Stefania Perri, G. Cororullo. Area-time-power tradeoff in cellular arrays VLSI implementations |
| 624 | -- | 629 | Antonio G. M. Strollo, E. Napoli, C. Cimino. Analysis of power dissipation in double edge-triggered flip-flops |
| 629 | -- | 633 | Chingwei Yeh, Yin-Shuin Kang. Cell-based layout techniques supporting gate-level voltage scaling for low power |
| 633 | -- | 636 | Krishnendu Chakrabarty, Brian T. Murray, Vikram Iyengar. Deterministic built-in test pattern generation for high-performance circuits using twisted-ring counters |