Table of Contents

• Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar DecodersZhen Gao, Ruize Wang, Haoyu Du, Pedro Reviriego. 1-6 [doi]
• Fine-Grained Vulnerability Analysis of Resource Constrained Neural Inference AcceleratorsPanayiotis Corneliou, Panagiota Nikolaou, Maria K. Michael, Theocharis Theocharides. 1-6 [doi]
• An Exploration of Microprocessor Self-Test Optimisation Based On Safe FaultsAnuraag Narang, Balaji Venn, S. Saqib Khursheed, Peter Harrod. 1-6 [doi]
• RADPlace: A Timing-aware RAdiation-Hardening Detailed Placement Scheme Satisfying TMR Spacing ConstraintsChristos Georgakidis, Iordanis Lilitsis, Georgios Stanimeropoulos, Christos P. Sotiriou. 1-6 [doi]
• JÄNES: A NAS Framework for ML-based EDA ApplicationsHardi Selg, Maksim Jenihhin, Peeter Ellervee. 1-6 [doi]
• SEU Evaluation of Hardened-by-Replication Software in RISC- V Soft ProcessorCorrado De Sio, Sarah Azimi, Andrea Portaluri, Luca Sterpone. 1-6 [doi]
• A Region-Based Bit-Shuffling Approach Trading Hardware Cost and Fault Mitigation EfficiencyRomain Mercier, Cédric Killian, Angeliki Kritikakou, Youri Helen, Daniel Chillet. 1-4 [doi]
• Mitigation of the impact of across chip systematic process variation using a novel system level designNabanita Ghoshal, Sree Rama K. C. Saraswatula, Santosh Yachareni, Shidong Zhou, Anil Kumar Kandala, Narendra Kumar Pulipati. 1-4 [doi]
• On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron TechnologiesPelopidas Tsoumanis, Georgios Ioannis Paliaroutis, Nestoras E. Evmorfopoulos, George I. Stamoulis. 1-6 [doi]
• Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAsIoanna Souvatzoglou, Athanasios Papadimitriou, Aitzan Sari, Vasileios Vlagkoulis, Mihalis Psarakis. 1-6 [doi]
• Zero-Overhead Protection for CNN WeightsStéphane Burel, Adrian Evans, Lorena Anghel. 1-6 [doi]
• Reliability Evaluation of Digital Channelizers Implemented on SRAM - FPGAsZhen Gao, Jiajun Xiao, Pedro Reviriego. 1-4 [doi]
• A Fault Model to Detect Design Errors in Combinational CircuitsPuneet Ramesh Savanur, Spyros Tragoudas. 1-4 [doi]
• Zoom-In Feature for Storage-Based Logic Built-In Self-TestIrith Pomeranz. 1-6 [doi]
• Usability-based Cross-Layer Reliability Evaluation of Image Processing ApplicationsCristiana Bolchini, Luca Cassano, Andrea Mazzeo, Antonio Miele. 1-6 [doi]
• Modeling Soft-Error Reliability Under VariabilityAneesh Balakrishnan, Guilherme Cardoso Medeiros, Cemil Cem Gürsoy, Said Hamdioui, Maksim Jenihhin, Dan Alexandrescu. 1-6 [doi]
• Non-invasive I2C Hardware Trojan Attack VectorMohamed Amine Khelif, Jordane Lorandel, Olivier Romain. 1-6 [doi]
• Fault Tolerance for Islandable-Microgrid SensorsVijay K. Jain, Glenn H. Chapman. 1-4 [doi]
• GF-Flush: A GF(2) Algebraic Attack on Dynamically Secured Scan ChainsDake Chen, Chunxiao Lin, Peter A. Beerel. 1-6 [doi]
• A Tunable Single Event Transient Filter Based on Digitally Controlled Capacitive Delay CellsMarko S. Andjelkovic, Oliver Schrape, Anselm Breitenreiter, Junchao Chen, Milos Krstic. 1-6 [doi]
• A Fault Tolerant soft-core obtained from an Interleaved-Multi- Threading RISC- V microprocessor designMarcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Francesco Vigli, Mauro Olivieri. 1-4 [doi]
• A Design of Reliable Linear FSMs with Equivalent States in Stochastic ComputingHideyuki Ichihara, Takayuki Fukuda, Tomoo Inoue. 1-6 [doi]
• A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural NetworksMarcel Merten, Sebastian Huhn 0001, Rolf Drechsler. 1-6 [doi]
• An In-Depth Vulnerability Analysis of RISC-V Micro-Architecture Against Fault Injection AttackZahra Kazemi, Amin Norollah, Afef Kchaou, Mahdi Fazeli, David Hély, Vincent Beroulle. 1-6 [doi]
• Testing and Reliability Enhancement of Security PrimitivesMd Toufiq Hasan Anik, Jean-Luc Danger, Omar Diankha, Mohammad Ebrahimabadi, Christoph Frisch, Sylvain Guilley, Naghmeh Karimi, Michael Pehl, Sofiane Takarabt. 1-8 [doi]
• Dependence of SEUs in Digital Cameras on Pixel size and ElevationGlenn H. Chapman, Simone Neufeld, Klinsmann J. Coelho Silva Meneses, Israel Koren, Zahava Koren, Coelho Silva Meneses. 1-4 [doi]
• Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW DesignDavide Bellizia, Nadia El Mrabet, Apostolos P. Fournaris, Simon Pontié, Francesco Regazzoni 0001, François-Xavier Standaert, Élise Tasso, Emanuele Valea. 1-6 [doi]
• Towards Fault Simulation at Mixed Register-Transfer/Gate-Level ModelsEndri Kaja, Nicolas Gerlin, Mounika Vaddeboina, Luis Rivas, Sebastian Prebeck, Zhao Han, Keerthikumara Devarajegowda, Wolfgang Ecker. 1-6 [doi]
• A Self-Healing, High Performance and Low-Cost Radiation Hardened Latch DesignSandeep Kumar, Atin Mukherjee 0001. 1-6 [doi]
• FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a ChipSébastien Thomet, Serge De Paoli, Jean-Marc Daveau, Valérie Bertin, Fady Abouzeid, Philippe Roche, Fakhreddine Ghaffari, Olivier Romain. 1-6 [doi]
• A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan HorsesAlessandro Palumbo, Luca Cassano, Pedro Reviriego, Giuseppe Bianchi 0001, Marco Ottavi. 1-6 [doi]
• Industrial best practice: cases of study by automotive chip- makersL. Degli Abbati, R. Ullmann, G. Paganini, M. Coppetta, L. Zaia, V. Huard, O. Montfort, R. Cantoro, G. Insinga, F. Venini, P. Calao, P. Bernardi. 1-6 [doi]
• The Impact of Faults on DNNs: A Case StudyElaheh Malekzadeh, Nezam Rohbani, Zhonghai Lu, Masoumeh Ebrahimi. 1-6 [doi]
• Static Timing Analysis Induced Simulation Errors for Asynchronous CircuitsStavros Simoglou, Christos P. Sotiriou, Nikolaos Blias. 1-4 [doi]
• An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory ComputingWei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li. 1-4 [doi]
• Reliability Assessment of Memristor based Gas Sensor ArrayVishal Gupta 0002, Giulio Panunzi, Saurabh Khandelwal, Eugenio Martinelli, Abusaleh M. Jabir, Marco Ottavi. 1-6 [doi]