Table of Contents

• Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety ApplicationsGabriele Boschi, Elisa Spano, Hayk T. Grigoryan, Arun Kumar, Gurgen Harutyunyan. 1-6 [doi]
• Modeling Novel Non-JTAG IEEE 1687-Like ArchitecturesMike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick. 1-10 [doi]
• Stress, Test, and Simulation of Analog IOs on Automotive ICsChen He, Stephen Traynor, Gayathri Bhagavatheeswaran, Hector Sanchez. 1-10 [doi]
• High Speed Serial Links Risk Assessment in Industrial Post-Silicon Validation Exploiting Machine Learning TechniquesCesar A. Sánchez-Martínez, Paulo López-Meyer, Esdras Juárez-Hernández, Aaron Desiga-Orenday, Andrés Viveros-Wacher. 1-5 [doi]
• Machine Learning based Performance Prediction of Microcontrollers using Speed MonitorsRiccardo Cantoro, Martin Huch, Tobias Kilian, Raffaele Martone, Ulf Schlichtmann, Giovanni Squillero. 1-5 [doi]
• TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble LearningLeon Li-Yang Chen, Katherine Shu-Min Li, Ken Chau-Cheung Cheng, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yen Tsai, Chen-Shiun Lee. 1-4 [doi]
• Multi-Level Access Protection for Future IEEE P1687.1 IJTAG NetworksDavid Brauchler, Jennifer Dworak. 1-10 [doi]
• Functional Test Sequences for Inducing Voltage Droops in a Multi-Threaded ProcessorVijay Kiran Kalyanam, Eric Mahurin, Michael Spence, Jacob A. Abraham. 1-10 [doi]
• Test and Diagnosis Solution for Functional SafetyM. Casarsa, Gurgen Harutyunyan, Yervant Zorian. 1-5 [doi]
• A Unified Method of Designing Signature Analyzers for Digital and Mixed-Signal Circuits TestingVadim Geurkov, Lev Kirischian. 1-5 [doi]
• Proactive Supply Noise Mitigation with Low-Latency Minor Voltage Regulator and Lightweight Current PredictionJun Chen, Masanori Hashimoto. 1-8 [doi]
• Schmitt Trigger-Based Key Provisioning for Locking Analog/RF Integrated CircuitsAdriana C. Sanabria-Borbon, Nithyashankari Gummidipoondi Jayasankaran, S. Y. Lee, Edgar Sánchez-Sinencio, J. Hu, Jeyavijayan J. V. Rajendran. 1-10 [doi]
• High Defect-Density Yield Learning using Three-Dimensional Logic Test ChipsZeye Liu 0001, R. D. Shawn Blanton. 1-10 [doi]
• Quick Analyses for Improving Reliability and Functional Safety of Mixed-Signal ICsStephen Sunter, Michal Wolinski, Anthony Coyette, Ronny Vanhooren, Wim Dobbelaere, Nektar Xama, Jhon Gomez, Georges G. E. Gielen. 1-10 [doi]
• A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer ReturnsS. Mhamdi, P. Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar. 1-10 [doi]
• A Weak Asynchronous RESet (ARES) PUF Using Start-up Characteristics of Null Conventional Logic GatesSreeja Chowdhury, Rabin Acharya, William Boullion, Andrew Felder, Mark Howard, Jia Di, Domenic Forte. 1-10 [doi]
• Improved Chain Diagnosis Methodology for Clock and Control Signal Defect IdentificationBharath Nandakumar, Sameer Chillarige, Anil Malik, Atul Chabbra, Nicholai L' Esperance, Robert Redburn. 1-9 [doi]
• Logic Fault Diagnosis of Hidden Delay DefectsStefan Holst, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, Xiaoqing Wen. 1-10 [doi]
• New Perspectives on Core In-field Path Delay TestRiccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan. 1-5 [doi]
• A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive DevicesChien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang. 1-9 [doi]
• Automated Socket Anomaly Detection through Deep LearningNidhi Agrawal, Min-Jian Yang, Constantinos Xanthopoulos, Vijayakumar Thangamariappan, Joe Xiao, Chee-Wah Ho, Keith Schaub, Ira Leventhal. 1-5 [doi]
• Automating Design For Yield: Silicon Learning to Predictive Models and Design OptimizationSrikanth Venkat Raman, Pongpachara Limpisathian, Pascal Meinerzhagen, Suriyaprakash Natarajan, Eric Yang. 1-10 [doi]
• Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space ChecksMd Imran Momtaz, Chandramouli N. Amarnath, Abhijit Chatterjee. 1-10 [doi]
• Modeling Accuracy of Wideband Power Amplifiers with Memory effects via MeasurementsWei Gao, Tao Jing. 1-7 [doi]
• Using Volume Cell-aware Diagnosis Results to Improve Physical Failure Analysis EfficiencyHanson Peng, Mao-Yuan Hsia, Man-Ting Pang, I.-Y. Chang, Jeff Fan, Huaxing Tang, Manish Sharma, Wu Yang. 1-4 [doi]
• Avionics Simulation EnvironmentHüseyin Sagirkaya, Gökhan Durgun. 1-3 [doi]
• Machine Intelligence for Efficient Test Pattern GenerationSoham Roy, Spencer K. Millican, Vishwani D. Agrawal. 1-5 [doi]
• Cross-PUF Attacks on Arbiter-PUFs through their Power Side-ChannelTrevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi. 1-5 [doi]
• Memory repair logic sharing techniques and their impact on yieldBenoit Nadeau-Dostie, Luc Romain. 1-5 [doi]
• Flip-flops fanout splitting in scan designsMaxim Ladnushkin. 1-5 [doi]
• Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital ConverterWei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang. 1-8 [doi]
• Assuring Security and Reliability of Emerging Non-Volatile MemoriesMohammad Nasim Imtiaz Khan, Swaroop Ghosh. 1-10 [doi]
• X-Tolerant Tunable Compactor for In-System TestYingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer, Bartosz Wldarczak. 1-10 [doi]
• Online Fault Detection in ReRAM-Based Computing Systems by Monitoring Dynamic Power ConsumptionMengyun Liu, Krishnendu Chakrabarty. 1-10 [doi]
• Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 InterfacesHaiying Ma, Ligang Lu, Haitao Qian, Jing Han, Xin Wen, Fanjin Meng, Rahul Singhal, Martin Keim, Yu Huang, Wu Yang. 1-5 [doi]
• FAT: Training Neural Networks for Reliable Inference Under Hardware FaultsUssama Zahid, Giulio Gambardella, Nicholas J. Fraser, Michaela Blott, Kees A. Vissers. 1-10 [doi]
• LAIDAR: Learning for Accuracy and Ideal Diagnostic ResolutionQicheng Huang, Chenlei Fang, R. D. Shawn Blanton. 1-10 [doi]
• Selecting Close-to-Functional Path Delay Faults for Test GenerationIrith Pomeranz. 1-5 [doi]
• Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event TransientsRafael B. Schvittz, Paulo F. Butzen, Leomar S. da Rosa. 1-9 [doi]
• Functional Criticality Classification of Structural Faults in AI AcceleratorsArjun Chaudhuri, Jonti Talukdar, Fei Su, Krishnendu Chakrabarty. 1-5 [doi]
• Introduction to Quantum Computation ReliabilityMitchell A. Thornton. 1-10 [doi]
• Fast EVM Tuning of MIMO Wireless Systems Using Collaborative Parallel Testing and Implicit Reward Driven LearningSuhasini Komarraju, Abhijit Chatterjee. 1-10 [doi]
• Robust DfT Techniques for Built-in Fault Detection in Operational Amplifiers with High CoverageMarampally Saikiran, Mona Ganji, Degang Chen. 1-10 [doi]
• Knowledge Transfer for Diagnosis Outcome Preview with Limited DataQicheng Huang, Chenlei Fang, R. D. Shawn Blanton. 1-9 [doi]
• Wafer Level Stress: Enabling Zero Defect Quality for Automotive Microcontrollers without Package Burn-InChen He, Yanyao Yu. 1-10 [doi]
• qATG: Automatic Test Generation for Quantum CircuitsChen-Hung Wu, Cheng-Yun Hsieh, Jiun-Yun Li, James Chien-Mo Li. 1-10 [doi]
• Security Preserving Integration and Resynthesis of Reconfigurable Scan NetworksNatalia Lylina, Ahmed Atteya, Chih-Hao Wang, Hans-Joachim Wunderlich. 1-10 [doi]
• Cost-Effective Test Method for screening out Unexpected Failure in High Speed Serial Interface IPsSang-Uck Ahn, Beom-Kyu Seo, Hyun Woo Kim, Yeoun-Sook Shin, Hyung-Tae Kim, Ghil-Geun Oh, Young Dae Kim. 1-4 [doi]
• Digital Design Techniques for Dependable High Performance ComputingSarah Azimi, Luca Sterpone. 1-10 [doi]
• Advanced Outlier Detection Using Unsupervised Learning for Screening Potential Customer ReturnsHanbin Hu, Nguyen Nguyen, Chen He, Peng Li 0001. 1-10 [doi]
• SPARTA: A Laser Probing Approach for Trojan DetectionAndrew Stern, Dhwani Mehta, Shahin Tajik, Farimah Farahmandi, Mark Mohammad Tehranipoor. 1-10 [doi]
• Design Optimization for N-port RF Network Reflectometers under Noise and Gain ImperfectionsMuslum Emir Avci, Sule Ozev. 1-10 [doi]
• Learning A Wafer Feature With One Training SampleYueling Jenny Zeng, Li-C. Wang, Chuanhe Jay Shan, Nik Sumikawa. 1-10 [doi]
• BISTLock: Efficient IP Piracy Protection using BISTSiyuan Chen, Jinwook Jung, Peilin Song, Krishnendu Chakrabarty, Gi-Joon Nam. 1-5 [doi]
• On the Measurement of Safe Fault Failure Rates in High-Performance Compute ProcessorsRichard Bramley, Yanxiang Huang, Guangshan Duan, Nirmal R. Saxena, Paul Racunas. 1-10 [doi]
• SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and ShortsSujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee. 1-10 [doi]
• Industrial Application of IJTAG Standards to the Test of Big-A/little-d devicesHans Martin von Staudt, Mohamed Anas Benhebibi, Jeff Rearick, Michael Laisne. 1-10 [doi]
• Fail Memory Configuration Set for RA EstimationHayoung Lee, Keewon Cho, Sungho Kang, Wooheon Kang, Seungtaek Lee, Woosik Jeong. 1-9 [doi]
• MBIST Supported Multi Step Trim for Reliable eMRAM SensingJongsin Yun, Benoit Nadeau-Dostie, Martin Keim, Lori Schramm, Cyrille Dray, El Mehdi Boujamaa, Khushal Gelda. 1-5 [doi]
• Concurrent Detection of Failures in GPU Control Logic for Reliable Parallel ComputingHiroaki Itsuji, Takumi Uezono, Tadanobu Toba, Kojiro Ito, Masanori Hashimoto. 1-5 [doi]
• Unsupervised Root-Cause Analysis for Integrated SystemsRenjian Pan, Zhaobo Zhang, Xin Li, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
• Novel Eye Diagram Estimation Technique to Assess Signal Integrity in High-Speed Memory TestYoungsu Oh, Dongmin Han, Byeongseon Go, Seungtaek Lee, Woosik Jeong. 1-5 [doi]
• Automated Assertion Generation from Natural Language SpecificationsSteven J. Frederiksen, John Aromando, Michael S. Hsiao. 1-5 [doi]
• Hardware IP Protection Using Logic Encryption and WatermarkingRajit Karmakar, Santanu Chattopadhyay. 1-10 [doi]
• Unleashing the Power of Anomaly Data for Soft Failure Predictive AnalyticsFei Su, Prashant Goteti, Min Zhang. 1-10 [doi]
• At-speed DfT Architecture for Bundled-data DesignRicardo Aquino Guazzelli, Laurent Fesquet. 1-9 [doi]
• Test Challenges of Intel IA CoresUri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin. 1-5 [doi]
• Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMsLizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui. 1-10 [doi]
• Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCsJean-François Côté, Mark Kassab, Wojciech Janiszewski, Ricardo Rodrigues, Reinhard Meier, Bartosz Kaczmarek, Peter Orlando, Geir Eide, Janusz Rajski, Glenn Colón-Bonet, Naveen Mysore, Ya Yin, Pankaj Pant. 1-10 [doi]
• IJTAG Through a Two-Pin Chip InterfaceManu Baby, Bernd Büttner, Piet Engelke, Ulrike Pfannkuchen, Reinhard Meier, Jonathan Gaudet, J.-F. Côté, Givargis Danialy, Martin Keim, Lori Schramm. 1-5 [doi]
• Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel ConfigurationsFong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang 0005, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada. 1-10 [doi]
• Data-driven fault model development for superconducting logicMingye Li, Fangzhou Wang, Sandeep K. Gupta. 1-5 [doi]