Masahiro Goshima - researchr alias

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Viewing Publication 1 - 38 from 38

2023

Out-of-Step Pipeline for Gather/Scatter InstructionsYi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima. date 2023: 1-2 [doi]

2019

An Open Source FPGA-Optimized Out-of-Order RISC-V Soft ProcessorSusumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima. icfpt 2019: 63-71 [doi]

2018

A Tightly Coupled Heterogeneous Core with Highly Efficient Low-Power ModeYasumasa Chidai, Kojiro Izuoka, Ryota Shioya, Masahiro Goshima, Hideki Ando. arcs 2018: 211-224 [doi]

An Analysis and a Solution of False Conflicts for Hardware Transactional MemoryYuki Futamase, Masaki Hayashi, Tomoki Tajimi, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura. icecsys 2018: 529-532 [doi]

Application of Timing Fault Detection to Rocket Core on FPGAUshio Jimbo, Ryota Shioya, Masahiro Goshima. ic-nc 2018: 178-181 [doi]

Isolation-Safe Speculative Access Control for Hardware Transactional MemoryTomoki Tajimi, Masaki Hayashi, Yuki Futamase, Ryota Shioya, Masahiro Goshima, Tomoaki Tsumura. icecsys 2018: 517-520 [doi]

Bank-Aware Instruction Scheduler for a Multibanked Register FileJunji Yamada, Ushio Jimbo, Ryota Shioya, Masahiro Goshima, Shuichi Sakai. jip, 26:696-705, 2018. [doi]

2017

2016

An Inductive Method to Select Simulation PointsMinseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai. ieicet, 99-D(12):2891-2900, 2016. [doi]

FXA: Executing Instructions in Front-End for Energy EfficiencyRyota Shioya, Ryo Takami, Masahiro Goshima, Hideki Ando. ieicet, 99-D(4):1092-1107, 2016. [doi]

2015

An Inductive Method to Select Simulation PointsMinseong Choi, Takashi Fukuda, Masahiro Goshima, Shuichi Sakai. ic-nc 2015: 392-395 [doi]

Address Order Violation Detection with Parallel Counting Bloom FiltersNaruki Kurata, Ryota Shioya, Masahiro Goshima, Shuichi Sakai. ieicet, 98-C(7):580-593, 2015. [doi]

2014

A cloud architecture for protecting guest's information from malicious operators with memory managementKoki Murakami, Tsuyoshi Yamada, Rie Shigetomi Yamaguchi, Masahiro Goshima, Shuichi Sakai. codaspy 2014: 155-158 [doi]

A Front-End Execution Architecture for High Energy EfficiencyRyota Shioya, Masahiro Goshima, Hideki Ando. micro 2014: 419-431 [doi]

2013

Register Indirect Jump Target ForwardingRyota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai. ieicet, 96-D(2):278-288, 2013. [doi]

2011

Low-Overhead Architecture for Security TagRyota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai. ieicet, 94-D(1):69-78, 2011. [doi]

2010

Register Cache System Not for Latency Reduction PurposeRyota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai. micro 2010: 301-312 [doi]

2009

String-Wise Information Flow Tracking against Script Injection AttacksKunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai. prdc 2009: 169-176 [doi]

Low-Overhead Architecture for Security TagRyota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai. prdc 2009: 135-142 [doi]

2008

Low-Complexity Bypass Network Using Small RAMShinobu Miwa, Hironori Ichibayashi, Hidetsugu Irie, Masahiro Goshima, Hironori Nakajo, Shinji Tomita. cdes 2008: 153-159

Ultra Dependable ProcessorShuichi Sakai, Masahiro Goshima, Hidetsugu Irie. ieicet, 91-C(9):1386-1393, 2008. [doi]

2007

Utilization of SECDED for soft error and variation-induced defect tolerance in cachesLuong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai. date 2007: 1134-1139 [doi]

Preventing timing errors on register writes: mechanisms of detections and recoveriesHidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai. sigarch, 35(5):25-31, 2007. [doi]

2006

SEVA: A Soft-Error- and Variation-Aware Cache ArchitectureLuong Dinh Hung, Masahiro Goshima, Shuichi Sakai. prdc 2006: 47-54 [doi]

Base Address Recognition with Data Flow Tracking for Injection Attack DetectionSatoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai. prdc 2006: 165-172 [doi]

2005

Mitigating Soft Errors in Highly Associative Cache with CAM-based TagLuong Dinh Hung, Masahiro Goshima, Shuichi Sakai. iccd 2005: 342-350 [doi]

2004

Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load BalancingMotohiro Takayama, Yuki Shinomoto, Masahiro Goshima, Shin-ichiro Mori, Yasuhiko Nakashima, Shinji Tomita. pdpta 2004: 373-382

2001

A high-speed dynamic instruction scheduling scheme for superscalar processorsMasahiro Goshima, Kengo Nishino, Toshiaki Kitamura, Yasuhiko Nakashima, Shinji Tomita, Shin-ichiro Mori. euromicro 2001: 225-236 [doi]

1999

A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPARAtsushi Kubota, Shogo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita. ijpp, 27(2):97-109, 1999.

1998

Optimized Code Generation for Heterogeneous Computing Environment using Parallelizing Compiler TINPARShin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita. IEEEpact 1998: 426-433 [doi]

1997

1995

A proposal of self-cleanup cacheShin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, Shinji Tomita. IEEEpact 1995: 298-301 [doi]

1993

A distributed shared memory multiprocessor ASURA: memory and cache architectureShin-ichiro Mori, Hideki Saito, Masahiro Goshima, Mamoru Yanagihara, Takashi Tanaka, David Fraser, Kazuki Joe, Hiroyuki Nitta, Shinji Tomita. sc 1993: 740-749 [doi]

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