Yuan Xie - researchr alias

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2011

Leakage Power and Circuit Aging Cooptimization by Gate Replacement TechniquesYu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. tvlsi, 19(4):615-628, 2011. [doi]

Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking ModelFeng Wang 0004, Yuan Xie. tdsc, 8(1):137-146, 2011. [doi]

Variation-Aware Task and Communication Mapping for MPSoC ArchitectureFeng Wang 0004, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. tcad, 30(2):295-307, 2011. [doi]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens, editors, ACM, 2011.

Impact of Circuit Degradation on FPGA Design SecurityHan-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan. isvlsi 2011: 230-235 [doi]

Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designsYibo Chen, Eren Kursun, Dave Motschman, Charles Johnson, Yuan Xie. islped 2010: 397-402 [doi]

Hybrid checkpointing using emerging nonvolatile memories for future exascale systemsXiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi. taco, 8(2):6, 2011. [doi]

AdaMS: Adaptive MLC/SLC phase-change memory design for file storageXiangyu Dong, Yuan Xie. aspdac 2011: 31-36 [doi]

Stacking magnetic random access memory atop microprocessors: an architecture-level evaluationXiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li. iet-cdt, 5(3):213-220, 2011. [doi]

On-chip hybrid power supply system for wireless sensor nodesWulong Liu, Yu Wang 0002, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang. aspdac 2011: 43-48 [doi]

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPsAsit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. isca 2011: 69-80 [doi]

Enabling architectural innovations using non-volatile memoryVijaykrishnan Narayanan, Vinay Saripalli, Karthik Swaminathan, Ravindhiran Mukundrajan, Guangyu Sun, Yuan Xie, Suman Datta. glvlsi 2011: 439-444 [doi]

F:::2:::BFLY: an on-chip free-space optical network with wavelength-switchingJin Ouyang, Chuan Yang, Dimin Niu, Yuan Xie, Zhiwen Liu. ics 2011: 348-358 [doi]

Enabling quality-of-service in nanophotonic network-on-chipJin Ouyang, Yuan Xie. aspdac 2011: 351-356 [doi]

MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchyShekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie. hpca 2011: 231-242 [doi]

Moguls: a model to explore the memory hierarchy for bandwidth improvementsGuangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen. isca 2011: 377-388 [doi]

A frequent-value based PRAM memory architectureGuangyu Sun, Dimin Niu, Jin Ouyang, Yuan Xie. aspdac 2011: 211-216 [doi]

Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance DegradationYu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. tdsc, 8(5):756-769, 2011. [doi]

Editorial- three-dimensional integrated circuits designYuan Xie, Pol Marchal. iet-cdt, 5(3):159, 2011. [doi]

Modeling, Architecture, and Applications for Emerging Memory TechnologiesYuan Xie. dt, 28(1):44-51, 2011. [doi]

2010

Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI ToleranceYiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy. tvlsi, 18(11):1621-1624, 2010. [doi]

Parametric yield driven resource binding in behavioral synthesis with multi-::::V::::::::::th::::::::::/V::::::::::dd:::::: libraryYibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach. aspdac 2010: 781-786 [doi]

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-::::V::::::::::th:::::: assignmentYibo Chen, Yuan Xie, Yu Wang 0002, Andrés Takach. aspdac 2010: 689-694 [doi]

Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysisYibo Chen, Dimin Niu, Yuan Xie, Krishnendu Chakrabarty. iccad 2010: 471-476 [doi]

3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memoryYibo Chen, Jishen Zhao, Yuan Xie. islped 2010: 55-60 [doi]

Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller SupportXiangyu Dong, Yuan Xie, Naveen Muralimanohar, Norman P. Jouppi. sc 2010: 1-11 [doi]

Fabrication Cost Analysis and Cost-Aware Design Space Exploration for 3-D ICsXiangyu Dong, Jishen Zhao, Yuan Xie. tcad, 29(12):1959-1972, 2010. [doi]

Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesisPaul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang 0002. aspdac 2010: 169-174 [doi]

Total Power Optimization for Combinational Logic Using Genetic AlgorithmsWei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. vlsisp, 58(2):145-160, 2010. [doi]

Energy- and endurance-aware design of phase change memory cachesYongsoo Joo, Dimin Niu, Xiangyu Dong, Guangyu Sun, Naehyuck Chang, Yuan Xie. date 2010: 136-141 [doi]

3D Stacked Microprocessor: Are We There Yet?Gabriel H. Loh, Yuan Xie. micro, 30(3):60-64, 2010. [doi]

Impact of process variations on emerging memristorDimin Niu, Yiran Chen, Cong Xu, Yuan Xie. dac 2010: 877-882 [doi]

Energy and performance driven circuit design for emerging phase-change memoryDimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie. aspdac 2010: 193-198 [doi]

Low-power dual-element memristor based memory designDimin Niu, Yiran Chen, Yuan Xie. islped 2010: 25-30 [doi]

Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chipJin Ouyang, Jing Xie, Matthew Poremba, Yuan Xie. iccad 2010: 477-482 [doi]

LOFT: A High Performance Network-on-Chip Providing Quality-of-Service SupportJin Ouyang, Yuan Xie. micro 2010: 409-420 [doi]

A Hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvementGuangyu Sun, Yongsoo Joo, Yibo Chen, Dimin Niu, Yuan Xie, Yiran Chen, Hai Li. hpca 2010: 1-12 [doi]

Cost-driven 3D integration with interconnect layersXiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li. dac 2010: 150-155 [doi]

Design exploration of hybrid caches with disparate memory technologiesXiaoxia Wu, Jian Li, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie. taco, 7(3):15, 2010. [doi]

Test-access mechanism optimization for core-based three-dimensional SOCsXiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie. mj, 41(10):601-615, 2010. [doi]

3D memory stacking for fast checkpointing/restore applicationsJing Xie, Xiangyu Dong, Yuan Xie. 3dic 2010: 1-6 [doi]

Processor Architecture Design Using 3D Integration TechnologyYuan Xie. vlsid 2010: 446-451 [doi]

A 3D SoC design for H.264 application with on-chip DRAM stackingTao Zhang, Kui Wang, Yi Feng 0003, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin. 3dic 2010: 1-6 [doi]

Cost-aware three-dimensional (3D) many-core multiprocessor designJishen Zhao, Xiangyu Dong, Yuan Xie. dac 2010: 126-131 [doi]

2009

Gate replacement techniques for simultaneous leakage and aging optimizationYu Wang 0002, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. date 2009: 328-333 [doi]

Variation-aware resource sharing and binding in behavioral synthesisFeng Wang 0004, Yuan Xie, Andres Takach. aspdac 2009: 79-84 [doi]

Networks-on-chip in emerging interconnect paradigms: Advantages and challengesLuca P. Carloni, Partha Pande, Yuan Xie. nocs 2009: 93-102 [doi]

Tolerating process variations in high-level synthesis using transparent latchesYibo Chen, Yuan Xie. aspdac 2009: 73-78 [doi]

A framework for estimating NBTI degradation of microarchitectural componentsMichael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. aspdac 2009: 455-460 [doi]

::::New-Age::::: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural ComponentsMichael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang 0002, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. ijpp, 37(4):417-431, 2009. [doi]

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systemsXiangyu Dong, Naveen Muralimanohar, Norman P. Jouppi, Richard Kaufmann, Yuan Xie. sc 2009: [doi]

System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)Xiangyu Dong, Yuan Xie. aspdac 2009: 234-241 [doi]

PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAMXiangyu Dong, Norman P. Jouppi, Yuan Xie. iccad 2009: 269-275 [doi]

Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICsBrent Hollosi, Tao Zhang, Ravi Sankar Parameswaran Nair, Yuan Xie, Jia Di, Scott Smith. 3dic 2009: 1-5 [doi]

Emerging technologies and their impact on system designNorman P. Jouppi, Yuan Xie. islped 2009: 427-428 [doi]

Guest Editors Introduction: Opportunities and Challenges of 3D IntegrationDavid S. Kung, Yuan Xie. dt, 26(5):4-5, 2009. [doi]

Temperature-Aware NBTI Modeling Techniques in Digital CircuitsHong Luo, Yu Wang 0002, Rong Luo, Huazhong Yang, Yuan Xie. ieicet, 92-C(6):875-886, 2009. [doi]

Process-Variation-Aware Adaptive Cache Architecture and ManagementMadhu Mutyam, Feng Wang 0004, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin. TC, 58(7):865-877, 2009. [doi]

CheckerCore: enhancing an FPGA soft core to capture worst-case execution timesJin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller. cases 2009: 175-184 [doi]

Arithmetic unit design using 180nm TSV-based 3D stacking technologyJin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin. 3dic 2009: 1-4 [doi]

Modeling Soft Errors at the Device and Logic Levels for Combinational CircuitsRajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jung Sub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu. tdsc, 6(3):202-216, 2009. [doi]

A criticality-driven microarchitectural three dimensional (3D) floorplannerSrinath Sridharan, Michael DeBole, Guangyu Sun, Yuan Xie, Vijaykrishnan Narayanan. aspdac 2009: 763-768 [doi]

Exploration of 3D stacked L2 cache design for high performance and efficient thermal controlGuangyu Sun, Xiaoxia Wu, Yuan Xie. islped 2009: 295-298 [doi]

A novel architecture of the 3D stacked MRAM L2 cache for CMPsGuangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen. hpca 2009: 239-249 [doi]

NBTI-aware statistical circuit delay assessmentBalaji Vaidyanathan, Anthony S. Oates, Yuan Xie, Yu Wang. isqed 2009: 13-18 [doi]

Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuningBalaji Vaidyanathan, Anthony S. Oates, Yuan Xie. iccad 2009: 164-171 [doi]

On the efficacy of input Vector Control to mitigate NBTI effects and leakage powerYu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang. isqed 2009: 19-26 [doi]

Power and performance of read-write aware Hybrid Caches with non-volatile memoriesXiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yuan Xie. date 2009: 737-742 [doi]

Scan-chain design and optimization for three-dimensional integrated circuitsXiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie. jetc, 5(2), 2009. [doi]

Hybrid cache architecture with disparate memory technologiesXiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ramakrishnan Rajamony, Yuan Xie. isca 2009: 34-45 [doi]

Statistical High-Level Synthesis under Process VariabilityYuan Xie, Yibo Chen. dt, 26(4):78-87, 2009. [doi]

3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC)Yaoyao Ye, Lian Duan, Jiang Xu, Jin Ouyang, Mo Kwai Hung, Yuan Xie. 3dic 2009: 1-6 [doi]

2008

A Variation Aware High Level Synthesis FrameworkFeng Wang 0004, Guangyu Sun, Yuan Xie. date 2008: 1063-1068 [doi]

Embedded Multi-Processor System-on-chip (MPSoC) design considering process variationsFeng Wang 0004, Yuan Xie. ipps 2008: 1-5 [doi]

Variability-driven module selection with joint design time optimization and post-silicon tuningFeng Wang 0004, Xiaoxia Wu, Yuan Xie. aspdac 2008: 2-9 [doi]

Technology, CAD tools, and designs for emerging 3D integration technologySyed M. Alam, Mike Ignatowski, Yuan Xie. glvlsi 2008: 1-2 [doi]

ILP-based scheme for timing variation-aware scheduling and resource bindingYibo Chen, Jin Ouyang, Yuan Xie. socc 2008: 27-30 [doi]

Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacementXiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen. dac 2008: 554-559 [doi]

Thermal-aware Design Considerations for Application-Specific Instruction Set ProcessorHai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam. sasp 2008: 63-68 [doi]

Thermal-aware reliability analysis for platform FPGAsPrasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan. iccad 2008: 722-727 [doi]

A low-power phase change memory based hybrid cache architecturePrasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim. glvlsi 2008: 395-398 [doi]

Power optimization for FinFET-based circuits using genetic algorithmsJin Ouyang, Yuan Xie. socc 2008: 211-214 [doi]

MIRA: A Multi-layered On-Chip Interconnect Router ArchitectureDongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. isca 2008: 251-261 [doi]

Hierarchical Soft Error Estimation Tool (HSEET)Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu. isqed 2008: 680-683 [doi]

Comparative analysis of NBTI effects on low power and high performance flip-flopsKrishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie. iccd 2008: 200-205 [doi]

Toward Increasing FPGA LifetimeSuresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari. tdsc, 5(2):115-127, 2008. [doi]

Design Space Exploration for 3-D CacheYuh-Fang Tsai, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. tvlsi, 16(4):444-455, 2008. [doi]

Two-dimensional crosstalk avoidance codesXuebin Wu, Zhiyuan Yan, Yuan Xie. sips 2008: 106-111 [doi]

Test-access mechanism optimization for core-based three-dimensional SOCsXiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie. iccd 2008: 212-218 [doi]

Editorial: Special issue on 3D integrated circuits and microarchitecturesYuan Xie, Jason Cong, Paul Franzon. jetc, 4(4), 2008. [doi]

Case Study of Reliability-Aware and Low-Power DesignShengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie. tvlsi, 16(7):861-873, 2008. [doi]

2007

Variation-aware task allocation and scheduling for MPSoCFeng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. iccad 2007: 598-603 [doi]

Code Compression for VLIW Embedded Systems Using a Self-Generating TableChang Hong Lin, Yuan Xie, Wayne Wolf. tvlsi, 15(10):1160-1171, 2007. [doi]

Processor Design in 3D Die-Stacking TechnologiesGabriel H. Loh, Yuan Xie, Bryan Black. micro, 27(3):31-48, 2007. [doi]

A Novel Gate-Level NBTI Delay Degradation Model with Stacking EffectHong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. patmos 2007: 160-170 [doi]

Variation Impact on SER of Combinational CircuitsKrishnan Ramakrishnan, R. Rajaraman, S. Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. isqed 2007: 911-916 [doi]

Architecting Microprocessor Components in 3D Design SpaceBalaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsid 2007: 103-108 [doi]

Scan chain design for three-dimensional integrated circuits (3D ICs)Xiaoxia Wu, Paul Falkenstern, Yuan Xie. iccd 2007: 208-214 [doi]

Reliability-aware Co-synthesis for Embedded SystemsYuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. vlsisp, 49(1):87-99, 2007. [doi]

Code Decompression Unit Design for VLIW Embedded ProcessorsYuan Xie, Wayne Wolf, Haris Lekatsas. tvlsi, 15(8):975-980, 2007. [doi]

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