Abstract is missing.
- The required technologies for Automotive towards 2020Udo Wolz. 1 [doi]
- An HDL-synthesized gated-edge-injection PLL with a current output DACDongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa. 2-3 [doi]
- An oscillator-based true random number generator with process and temperature toleranceTakehiko Amaki, Masanori Hashimoto, Takao Onoye. 4-5 [doi]
- Implementation of double arbiter PUF and its performance evaluation on FPGATakanori Machida, Dai Yamamoto, Mitsugu Iwamoto, Kazuo Sakiyama. 6-7 [doi]
- A negative-resistance sense amplifier for low-voltage operating STT-MRAMYohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii. 8-9 [doi]
- A high stability, low supply voltage and low standby power six-transistor CMOS SRAMNobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto. 10-11 [doi]
- An efficient multi-port memory controller for multimedia applicationsXuan-Thuan Nguyen, Cong-Kha Pham. 12-13 [doi]
- Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesisMasanori Hashimoto, Dawood Alnajiar, Hiroaki Konoura, Yukio Mitsuyama, Hajime Shimada, Kazutoshi Kobayashi, Hiroyuki Kanbara, Hiroyuki Ochi, Takashi Imagawa, Kazutoshi Wakabayashi, Takao Onoye, Hidetoshi Onodera. 14-15 [doi]
- A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systemsYozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshimoto. 16-17 [doi]
- A 128-way FPGA platform for the acceleration of KLMS algorithmXiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren. 18-19 [doi]
- A real-time permutation entropy computation for EEG signalsXiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren. 20-21 [doi]
- A high efficient hardware architecture for multiview 3DTVJiang Yu, Geng Liu, Xin Zhang, Pengju Ren. 22-23 [doi]
- Design of a scalable many-core processor for embedded applicationsHsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou. 24-25 [doi]
- A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensorDaisuke Fujimoto, Noriyuki Miura, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata. 26-27 [doi]
- A 64×64 1200fps dual-mode CMOS ion-image sensor for accurate DNA sequencingXiwei Huang, Jing Guo, Mei Yan, Hao Yu. 28-29 [doi]
- A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvestersToshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa. 30-31 [doi]
- Dual-output wireless power delivery system for small size large volume wireless memory cardJunki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro. 32-33 [doi]
- A tri-level 50MS/s 10-bit capacitive-DAC for Bluetooth applicationsDaisuke Kanemoto, Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya. 34-35 [doi]
- A tail-current modulated VCO with adaptive-bias schemeAravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa. 36-37 [doi]
- A Low-Power VCO based ADC with asynchronous sigma-delta modulator in 65nm CMOSJili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin. 38-39 [doi]
- A 0.5-V 5.8-GHz low-power asymmetrical QPSK/OOK transceiver for wireless sensor networkSho Ikeda, Sang-yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. 40-41 [doi]
- A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detectionTeerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa. 42-43 [doi]
- Circuit and package design for 44GB/s inductive-coupling DRAM/SoC interfaceAkira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda. 44-45 [doi]
- Design and analysis for ThruChip design for manufacturing (DFM)Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda. 46-47 [doi]
- A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architecturesLeibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, Jie Han. 48-53 [doi]
- Adaptive remaining hop count flow control: Consider the interaction between packetsPeng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li. 54-60 [doi]
- A flexible hardware barrier mechanism for many-core processorsTakeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue. 61-68 [doi]
- A performance enhanced dual-switch Network-on-Chip architectureLian Zeng, Takahiro Watanabe. 69-74 [doi]
- A cross-layer framework for designing and optimizing deeply-scaled FinFET-based SRAM cells under process variationsAlireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram. 75-80 [doi]
- Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOIAdam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg. 81-86 [doi]
- Microarchitectural-level statistical timing models for near-threshold circuit designJun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 87-93 [doi]
- Stress-aware P/G TSV planning in 3D-ICsShengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi Baradaran Tahoori. 94-99 [doi]
- Quantitative modeling of racetrack memory, a tradeoff among area, performance, and powerChao Zhang, Guangyu Sun, Weiqi Zhang, Fan Mi, Hai Li, Weisheng Zhao. 100-105 [doi]
- Technological exploration of RRAM crossbar array for matrix-vector multiplicationPeng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang. 106-111 [doi]
- Modeling framework for cross-point resistive memory design emphasizing reliability and variability issuesYang Zheng, Cong Xu, Yuan Xie 0001. 112-117 [doi]
- A defect-aware approach for mapping reconfigurable Single-Electron Transistor arraysChing-Yi Huang, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan. 118-123 [doi]
- Powering the IoT: Storage-less and converter-less energy harvestingHyung Gyu Lee, Naehyuck Chang. 124-129 [doi]
- Distributed computing in IoT: System-on-a-chip for smart cameras as an exampleShao-Yi Chien, Wei-Kai Chan, Yu-Hsiang Tseng, Chia-han Lee, V. Srinivasa Somayazulu, Yen-Kuang Chen. 130-135 [doi]
- Data sensing and analysis: Challenges for wearablesJames Williamson, Qi Liu, Fenglong Lu, Wyatt Mohrman, Kun Li, Robert P. Dick, Li Shang. 136-141 [doi]
- ShuttleNoC: Boosting on-chip communication efficiency by enabling localized power adaptationHang Lu, Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li. 142-147 [doi]
- Energy-efficient optical crossbars on chip with multi-layer deposited siliconHui Li, Sébastien Le Beux, Gabriela Nicolescu, Ian O'Connor. 148-153 [doi]
- Two-phase protocol converters for 3D asynchronous 1-of-n data linksJulian J. H. Pontes, Pascal Vivet, Yvain Thonnart. 154-159 [doi]
- Fine-grained runtime power budgeting for networks-on-chipXiaohang Wang, Tengfei Wang, Terrence S. T. Mak, Mei Yang, Yingtao Jiang, Masoud Daneshtalab. 160-165 [doi]
- Nonvolatile memory allocation and hierarchy optimization for high-level synthesisShuangchen Li, Ang Li, Yongpan Liu, Yuan Xie 0001, Huazhong Yang. 166-171 [doi]
- Reverse BDD-based synthesis for splitter-free optical circuitsRobert Wille, Oliver Keszocze, Clemens Hopfmuller, Rolf Drechsler. 172-177 [doi]
- Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuitsAaron Lye, Robert Wille, Rolf Drechsler. 178-183 [doi]
- Design and optimization of 3D digital microfluidic biochips for the polymerase chain reactionZipeng Li, Tsung-Yi Ho, Krishnendu Chakrabarty. 184-189 [doi]
- An accurate and low-cost PM2.5 estimation method based on Artificial Neural NetworkLixue Xia, Rong Luo, Bin Zhao, Yu Wang, Huazhong Yang. 190-195 [doi]
- Iterative disparity voting based stereo matching algorithm and its hardware implementationZhi Hu, Yibo Fan, Xiaoyang Zeng. 196-201 [doi]
- Obstacle-avoiding wind turbine placement for power-loss and wake-effect optimizationYu-Wei Wu, Yi-Yu Shi, Sudip Roy, Tsung-Yi Ho. 202-207 [doi]
- An efficient linear time triple patterning solverHaitong Tian, Hongbo Zhang, Zigang Xiao, Martin D. F. Wong. 208-213 [doi]
- Gate sizing and threshold voltage assignment for high performance microprocessor designsTiago Reimann, Cliff C. N. Sze, Ricardo Reis. 214-219 [doi]
- Analytical placement for rectilinear blocksYasuhiro Takashima. 220-225 [doi]
- IR to routing challenge and solution for interposer-based designEric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang. 226-230 [doi]
- Aging mitigation in memory arrays using self-controlled bit-flipping techniqueAnteneh Gebregiorgis, Mojtaba Ebrahimi, Saman Kiamehr, Fabian Oboril, Said Hamdioui, Mehdi Baradaran Tahoori. 231-236 [doi]
- Design methodology for approximate accumulator based on statistical error modelChang Liu, Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang. 237-242 [doi]
- Multiple Independent Gate FETs: How many gates do we need?Luca Gaetano Amarù, Gage Hills, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli. 243-248 [doi]
- Polynomial time algorithm for area and power efficient adder synthesis in high-performance designsSubhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan. 249-254 [doi]
- Accelerating SAT-based Boolean matching for heterogeneous FPGAs using one-hot encoding and CEGAR techniqueYusuke Matsunaga. 255-260 [doi]
- Negotiation-based task scheduling and storage control algorithm to minimize user's electric bills under dynamic pricesJi Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram. 261-266 [doi]
- Many-to-many active cell balancing strategy designMatthias Kauer, Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz, Samarjit Chakraborty. 267-272 [doi]
- Intra-vehicle network routing algorithm for wiring weight and wireless transmit power minimizationTa-Yang Huang, Chia-Jui Chang, Chung-Wei Lin, Sudip Roy, Tsung-Yi Ho. 273-278 [doi]
- An autonomous decentralized mechanism for energy interchanges with accelerated diffusion based on MCMCYusuke Sakumoto, Ittetsu Taniguchi. 279-284 [doi]
- ASP-DAC 2015 keynote speech II programmable networkAtsushi Takahara. 285 [doi]
- Machine learning and pattern matching in physical designBei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng. 286-293 [doi]
- Self-learning and adaptive board-level functional fault diagnosisFangming Ye, Krishnendu Chakrabarty, Zhaobo Zhang, Xinli Gu. 294-301 [doi]
- Fast statistical analysis of rare failure events for memory circuits in high-dimensional variation spaceShupeng Sun, Xin Li. 302-307 [doi]
- Data mining in functional test content optimizationLi-C. Wang. 308-315 [doi]
- Checkpoint-aware instruction scheduling for nonvolatile processor with multiple functional unitsMimi Xie, Chen Pan, Jingtong Hu, Chengmo Yang, Yiran Chen. 316-321 [doi]
- Balloonfish: Utilizing morphable resistive memory in mobile virtualizationLinbo Long, Duo Liu, Xiao Zhu, Kan Zhong, Zili Shao, Edwin Hsing-Mean Sha. 322-327 [doi]
- A three-stage-write scheme with flip-bit for PCM main memoryYanbin Li, Xin Li 0002, Lei Ju, Zhiping Jia. 328-333 [doi]
- A Garbage Collection Aware Stripping method for Solid-State DrivesMin Huang, Yi Wang, Zhaoqing Liu, Liyan Qiao, Zili Shao. 334-339 [doi]
- Unified non-volatile memory and NAND flash memory architecture in smartphonesRenhai Chen, Yi Wang, Jingtong Hu, Duo Liu, Zili Shao, Yong Guan. 340-345 [doi]
- A retargetable and accurate methodology for logic-IP-internal electromigration assessmentPalkesh Jain, Sachin S. Sapatnekar, Jordi Cortadella. 346-351 [doi]
- New electromigration modeling and analysis considering time-varying temperature and current densitiesHai-Bao Chen, Sheldon X.-D. Tan, Xin Huang, Valeriy Sukharev. 352-357 [doi]
- Generating circuit current constraints to guarantee power grid safetyZahi Moudallal, Farid N. Najm. 358-365 [doi]
- BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategiesAadithya V. Karthik, Sayak Ray, Jaijeet Roychowdhury. 366-371 [doi]
- A fast parallel approach for common path pessimism removalChung-Hao Tsai, Wai-Kei Mak. 372-377 [doi]
- Detailed-Routing-Driven analytical standard-cell placementChau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang. 378-383 [doi]
- An approach to anchoring and placing high performance custom digital designsShih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen. 384-389 [doi]
- Non-stitch triple patterning-aware routing based on conflict graph pre-coloringPo-Ya Hsu, Yao-Wen Chang. 390-395 [doi]
- Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routingShao-Yun Fang. 396-401 [doi]
- A length matching routing method for disordered pins in PCB designRan Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe. 402-407 [doi]
- Systems modeling for additional development in automotive E/E architectureHidekazu Nishimura. 408-409 [doi]
- Implementation and evaluation of image recognition algorithm for an intelligent vehicle using heterogeneous multi-core SoCNau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno. 410-415 [doi]
- Trend in power devices for electric and hybrid electric vehiclesKhalid Hussein, Akira Fujita, Katsumi Sato. 416 [doi]
- Multilane Racetrack caches: Improving efficiency through compression and independent shiftingHaifeng Xu, Yong Li, Rami G. Melhem, Alex K. Jones. 417-422 [doi]
- Managing hybrid on-chip scratchpad and cache memories for multi-tasking embedded systemsZimeng Zhou, Lei Ju, Zhiping Jia, Xin Li. 423-428 [doi]
- Optimizing thread-to-core mapping on manycore platforms with distributed Tag DirectoriesGuantao Liu, Tim Schmidt, Rainer Dömer, Ajit Dingankar, Desmond Kirkpatrick. 429-434 [doi]
- Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systemsMohammad Shihabul Haque, Ang Li, Akash Kumar, Qingsong Wei. 435-440 [doi]
- Accurate passivity-enforced macromodeling for RF circuits via iterative zero/pole update based on measurement dataYing-Chih Wang, Shihui Yin, Minhee Jun, Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi. 441-446 [doi]
- Physical verification flow for hierarchical analog ic design constraintsVolker Meyer zu Bexten, Markus Tristl, Göran Jerke, Hartmut Marquardt, Dina Medhat. 447-453 [doi]
- Automatic design for analog/RF front-end system in 802.11ac receiverZhijian Pan, Chuan Qin, Zuochang Ye, Yan Wang. 454-459 [doi]
- SIPredict: Efficient post-layout waveform prediction via System IdentificationQicheng Huang, Xiao Li, Fan Yang, Xuan Zeng, Xin Li. 460-465 [doi]
- Useful clock skew scheduling using adjustable delay buffers in multi-power mode designsJuyeon Kim, Taewhan Kim. 466-471 [doi]
- Fast clock skew scheduling based on sparse-graph algorithmsRickard Ewetz, Shankarshana Janarthanan, Cheng-Kok Koh. 472-477 [doi]
- Modeling and optimization of low power resonant clock meshWulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang. 478-483 [doi]
- Synthesis of resonant clock networks supporting dynamic voltage / frequency scalingSeyong Ahn, Minseok Kang, Marios C. Papaefthymiou, Taewhan Kim. 484-489 [doi]
- An efficient STT-RAM-based register file in GPU architecturesXiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen. 490-495 [doi]
- A bit-write reduction method based on error-correcting codes for non-volatile memoriesMasashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa. 496-501 [doi]
- Minimizing MLC PCM write energy for free through profiling-based state remappingMengying Zhao, Yuan Xue, Chengmo Yang, Chun Jason Xue. 502-507 [doi]
- Improving performance and lifetime of DRAM-PCM hybrid main memory through a proactive page allocation strategyHoda Aghaei Khouzani, Chengmo Yang, Jingtong Hu. 508-513 [doi]
- Enhanced LCCG: A novel test clock generation scheme for faster-than-at-speed delay testingSongwei Pei, Ye Geng, Huawei Li, Jun Liu, Song Jin. 514-519 [doi]
- An efficient 3D-IC on-chip test framework to embed TSV testing in memory BISTLiang-Che Li, Wen-Hsuan Hsu, Kuen-Jong Lee, Chun-Lung Hsu. 520-525 [doi]
- An integrated temperature-cycling acceleration and test technique for 3D stacked ICsNima Aghaee, Zebo Peng, Petru Eles. 526-531 [doi]
- Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAMSergej Deutsch, Krishnendu Chakrabarty. 532-537 [doi]
- Logic-DRAM co-design to efficiently repair stacked DRAM with unused sparesMinjie Lv, Hongbin Sun, Jingmin Xin, Nanning Zheng. 538-543 [doi]
- Electromigration-aware redundant via insertionJiwoo Pak, Bei Yu, David Z. Pan. 544-549 [doi]
- Synthesis of resilient circuits from guarded atomic actionsYuankai Chen, Hai Zhou. 550-555 [doi]
- Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuitsYen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He. 556-561 [doi]
- ASP-DAC 2015 keynote speech III: When and how will an AI be smart enough to design?Noriko Arai. 562 [doi]
- Toward large-scale access-transistor-free memristive crossbarsAmirali Ghofrani, Miguel Angel Lastras-Montano, Kwang-Ting Cheng. 563-568 [doi]
- Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile LogicsMeng-Fan Chang, Albert Lee, Chien-Chen Lin, Mon-Shu Ho, Ping-Cheng Chen, Chia-Chen Kuo, Ming-Pin Chen, Pei-Ling Tseng, Tzu-Kun Ku, Chien-Fu Chen, Kai-Shin Li, Jia-Min Shieh. 569-574 [doi]
- TM) Selector technology for super-dense, low power, low latency data storage systemsSung Hyun Jo, Tanmay Kumar, Mehdi Asnaashari, Wei D. Lu, Hagop Nazarian. 575 [doi]
- Modeling and design optimization of ReRAMJ. F. Kang, H. T. Li, P. Huang, Z. Chen, B. Gao, X. Y. Liu, Z. Z. Jiang, H.-S. P. Wong. 576-581 [doi]
- Evaluation of runtime monitoring methods for real-time event streamsBiao Hu, Kai Huang, Gang Chen, Alois Knoll. 582-587 [doi]
- Automatic timing-coherent transactor generation for mixed-level simulationsLi-Chun Chen, Hsin-I. Wu, Ren-Song Tsay. 588-593 [doi]
- Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environmentsHsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, Jean Tsao, Shih-Chieh Chang. 594-599 [doi]
- SWAT: Assertion-based debugging of concurrency issues at system levelLuis Gabriel Murillo, Robert Lajos Bucs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid. 600-605 [doi]
- Communication protocol analysis of transaction-level models using Satisfiability Modulo TheoriesChe-Wei Chang, Rainer Dömer. 606-611 [doi]
- Guiding fault-driven adaption in multicore systems through a reliability-aware static task scheduleLaura A. Rozo Duque, Chengmo Yang. 612-617 [doi]
- Approximation-aware scheduling on heterogeneous multi-core architecturesCheng Tan, Thannirmalai Somu Muthukaruppan, Tulika Mitra, Lei Ju. 618-623 [doi]
- Composing real-time applications from communicating black-box componentsMartin Becker 0001, Alejandro Masrur, Samarjit Chakraborty. 624-629 [doi]
- Enhanced partitioned scheduling of Mixed-Criticality Systems on multicore platformsZaid Al-bayati, Qingling Zhao, Ahmed Youssef, Haibo Zeng, Zonghua Gu. 630-635 [doi]
- Reducing Dynamic Dispatch Overhead (DDO) of SLDL-synthesized embedded softwareJiaxing Zhang, Sanyuan Tang, Gunar Schirner. 636-643 [doi]
- Contact pitch and location prediction for Directed Self-Assembly template verificationZigang Xiao, Yuelin Du, Martin D. F. Wong, He Yi, H.-S. Philip Wong, Hongbo Zhang. 644-651 [doi]
- Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithographyYunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou. 652-657 [doi]
- Polynomial time optimal algorithm for stencil row planning in e-beam lithographyDaifeng Guo, Yuelin Du, Martin D. F. Wong. 658-664 [doi]
- Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithographyYukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka. 665-670 [doi]
- Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterningShao-Yun Fang, Yi-Shu Tai, Yao-Wen Chang. 671-676 [doi]
- The prospects of next generation television - Japan's initiative to 2020Keiya Motohashi. 677-679 [doi]
- 8K LCD: Technologies and challenges toward the realization of SUPER Hi-VISION TVTakeshi Kumakura. 680-683 [doi]
- The world's 1st Complete-4K SoC solution with hybrid memory systemDaisuke Murakami, Yuki Soga, Daisuke Imoto, Yoshiharu Watanabe, Takashi Yamada. 684-686 [doi]
- H.265/HEVC encoder for UHDTVMitsuo Ikeda. 687-688 [doi]
- An accurate ACOSSO metamodeling technique for processor architecture design space explorationHongwei Wang, Ziyuan Zhu, Jinglin Shi, Yongtao Su. 689-694 [doi]
- Speeding up single pass simulation of PLRUt cachesJosef Schneider, Jorgen Peddersen, Sri Parameswaran. 695-700 [doi]
- ADAPT: An adaptive manycore methodology for software pipelined applicationsXi Zhang, Haris Javaid, Muhammad Shafique, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran. 701-706 [doi]
- A trace-driven approach for fast and accurate simulation of manycore architecturesAnastasiia Butko, Rafael Garibotti, Luciano Ost, Vianney Lapotre, Abdoulaye Gamatié, Gilles Sassatelli, Chris Adeniyi-Jones. 707-712 [doi]
- Compact modeling of microbatteries using behavioral linearization and model-order reductionMohammed Shemsu Nesro, Lizhong Sun, Ibrahim M. Elfadel. 713-718 [doi]
- GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solverYan Zhu, Sheldon X.-D. Tan. 719-724 [doi]
- Automated generation of hybrid system models for reachability analysis of nonlinear analog circuitsHyun-Sek Lukas Lee, Matthias Althoff, Stefan Hoelldampf, Markus Olbrich, Erich Barke. 725-730 [doi]
- Area efficient device-parameter estimation using sensitivity-configurable ring oscillatorShoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye. 731-736 [doi]
- On test syndrome merging for reasoning-based board-level functional fault diagnosisZelong Sun, Li Jiang, Qiang Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu. 737-742 [doi]
- Event-driven transient error propagation: A scalable and accurate soft error rate estimation approachMojtaba Ebrahimi, Razi Seyyedi, Liang Chen, Mehdi Baradaran Tahoori. 743-748 [doi]
- A novel methodology for testing hardware security and trust exploiting On-Chip Power noise MeasurementDaisuke Fujimoto, Makoto Nagata, Shivam Bhasin, Jean-Luc Danger. 749-754 [doi]
- Hardware Trojan detection using exhaustive testing of k-bit subspacesNicole Lesperance, Shrikant Kulkarni, Kwang-Ting Cheng. 755-760 [doi]
- AROMA: A highly accurate microcomponent-based approach for embedded processor power analysisZih-Ci Huang, Chi-Kang Chen, Ren-Song Tsay. 761-766 [doi]
- Battery-aware mapping optimization of loop nests for CGRAsYu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei. 767-772 [doi]
- THOR: Orchestrated thermal management of cores and networks in 3D many-core architecturesJinho Lee, Junwhan Ahn, Kiyoung Choi, Kyungsu Kang. 773-778 [doi]
- Early stage real-time SoC power estimation using RTL instrumentationJianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai. 779-784 [doi]
- Heterogeneous architecture design with emerging 3D and non-volatile memory technologiesQiaosha Zou, Matthew Poremba, Rui He, Wei Yang, Junfeng Zhao, Yuan Xie 0001. 785-790 [doi]
- Alleviate chip I/O pin constraints for multicore processors through optical interconnectsZhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H. K. Duong, Zhifei Wang, Haoran Li, Rafael Kioji Vivas Maeda, Xiaowen Wu, Yaoyao Ye, Qinfen Hao. 791-796 [doi]
- A fast and accurate network-on-chip timing simulator with a flit propagation modelTing-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, Jing-Jia Liou. 797-802 [doi]
- Application-level embedded communication tracer for many-core systemsChih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien. 803-808 [doi]
- Timing-based anomaly detection in embedded systemsSixing Lu, Minjun Seo, Roman Lysecky. 809-814 [doi]
- Satisfiability Don't Care condition based circuit fingerprinting techniquesCarson Dunbar, Gang Qu. 815-820 [doi]
- IC Piracy prevention via Design Withholding and EntanglementSoroush Khaleghi, Kai Da Zhao, Wenjing Rao. 821-826 [doi]
- Vulnerability analysis for crypto devices against probing attackLingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu, Junfeng Fan, Qiang Xu. 827-832 [doi]