Abstract is missing.
- Self-repairing and tuning reconfigurable electronics for spaceDidier Keymeulen. 1 [doi]
- Safety features of SoCs: How can they be re-used?Davide Appello. 2 [doi]
- Asynchronous design, Quo Vadis?Alex Yakovlev. 3 [doi]
- Formal verification meets robustness checking - Techniques and challengesRolf Drechsler, Görschwin Fey. 4 [doi]
- Evolutionary circuit design: TutorialLukás Sekanina. 5 [doi]
- Ensuring high testability without degrading security: Embedded tutorial on "test and security"Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 6 [doi]
- Advanced embedded memory testing: Reducing the defect per million level at lower test costSaid Hamdioui, A. J. van de Goor. 7 [doi]
- Automated simulation-based verification of power requirements for Systems-on-ChipsChristoph Trummer, Christoph M. Kirchsteiger, Christian Steger, Reinhold Weiss, Markus Pistauer, Damian Dalton. 8-11 [doi]
- Noise determination of a current conveyor in an inverting voltage amplifier configurationStylianos Siskos. 12-15 [doi]
- Utilizing the Bulk-driven technique in analog circuit designFabian Khateb, Dalibor Biolek, Nabhan Khatib, Jiri Vavra. 16-19 [doi]
- Instruction reliability analysis for embedded processorsAli Azarpeyvand, Mostafa E. Salehi, Farshad Firouzi, Amir Yazdanbakhsh, Sied Mehdi Fakhraie. 20-23 [doi]
- Automated SEU fault emulation using partial FPGA reconfigurationUros Legat, Anton Biasizzo, Franc Novak. 24-27 [doi]
- Low-cost fault tolerance on the ALU in simple pipelined processorsNguyen Minh Huu, Bruno Robisson, Michel Agoyan, Nathalie Drach. 28-31 [doi]
- Design of a single layer programmable Structured ASIC libraryThomas C. P. Chau, David W. L. Wu, Yanqing Ai, Brian P. W. Chan, Sam M. H. Ho, Oscar K. L. Lau, Steve C. L. Yuen, Kong-Pang Pun, Oliver C. S. Choy, Philip Heng Wai Leong. 32-35 [doi]
- On the mitigation of SET broadening effects in integrated circuitsLuca Sterpone, Niccolò Battezzati. 36-39 [doi]
- A software-based self-test and hardware reconfiguration solution for VLIW processorsTobias Koal, Heinrich Theodor Vierhaus. 40-43 [doi]
- A low power low voltage mixer for 2.4GHz applications in CMOS-90nm technologyAlberto Villegas, Diego Vázquez, Adoración Rueda. 44-47 [doi]
- Characterization of randomness sources in ring oscillator-based true random number generators in FPGAsBoyan Valtchanov, Viktor Fischer, Alain Aubert, Florent Bernard. 48-53 [doi]
- Efficient mapping of nondeterministic automata to FPGA for fast regular expression matchingJan Korenek, Vlastimil Kosar. 54-59 [doi]
- Data compression in hardware - The Burrows-Wheeler approachSebastian Arming, Roman Fenkhuber, Thomas Handl. 60-65 [doi]
- Software-based self-repair of statically scheduled superscalar data pathsMario Schölzel. 66-71 [doi]
- Built-in Clock Domain Crossing (CDC) test and diagnosis in GALS systemsCarlos Leong, Pedro Machado, Vasco Bexiga, João Paulo Teixeira, Isabel C. Teixeira, J. C. Silva, Pedro Lousã, João Varela. 72-77 [doi]
- A better-than-worst-case robustness measureStefan Frehse, Görschwin Fey, Rolf Drechsler. 78-83 [doi]
- An integrated low power buck converter with a comparator controlled low-side switchReinhard Enne, Horst Zimmermann. 84-87 [doi]
- A Build-In Self-Test technique for RF MixersLambros Dermentzoglou, Angela Arapoyanni, Yiorgos Tsiatouhas. 88-92 [doi]
- Ultra low-voltage bidirectional current mirror using clocked semi-floating-gate transistorsYngvar Berg. 93-98 [doi]
- Combining de-stressing and self repair for long-term dependable systemsTobias Koal, Heinrich Theodor Vierhaus. 99-104 [doi]
- Developing reconfigurable FIFOs to optimize power/performance of Voltage/Frequency Island-based networks-on-chipAmir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 105-110 [doi]
- Exploration of the FlexRay signal integrity using a combined prototyping and simulation approachMartin Krammer, Federico Clazzer, Eric Armengaud, Michael Karner, Christian Steger, Reinhold Weiss. 111-116 [doi]
- Self-Adaptive mechanism for cache memory reliability improvementLiviu Agnola, Mircea Vladutiu, Mihai Udrescu. 117-118 [doi]
- Design - Time configurable processor basic structureFilip Adamec, Tomas Fryza. 119-120 [doi]
- Reconfigurable hardware objects for image processing on FPGAsJan Kloub, Petr Honzík, Martin Danek. 121-122 [doi]
- A 65nm embedded low power SRAM compilerSheng Wu, Xiang Zheng, Zhiqiang Gao, Xiangqing He. 123-124 [doi]
- Blind image deconvolution algorithm on NVIDIA CUDA platformTomas Mazanec, Antonin Hermanek, Jan Kamenický. 125-126 [doi]
- Partitioning methods for unicast/multicast traffic in 3D NoC architectureMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen. 127-132 [doi]
- SystemC-AMS SDF model synthesis for exploration of heterogeneous architecturesAndreas Popp, Andreas Herrholz, Kim Grüttner, Yannick Le Moullec, Peter Koch, Wolfgang Nebel. 133-138 [doi]
- A fault-tolerant and congestion-aware routing algorithm for Networks-on-ChipMojtaba Valinataj, Siamak Mohammadi, Juha Plosila, Pasi Liljeberg. 139-144 [doi]
- Current Sensing Completion Detection in deep sub-micron technologiesLukás Nagy, Viera Stopjaková. 145-148 [doi]
- Hardware accelerated pattern matching based on Deterministic Finite Automata with perfect hashingJan Kastil, Jan Korenek. 149-152 [doi]
- Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receiversMehmood-ur-Rehman Awan, Peter Koch. 153-156 [doi]
- A 3-5GHz UWB CMOS receiver with digital control techniqueBo Han, Mengmeng Liu, Ning Ge. 157-160 [doi]
- Computation reduction for statistical analysis of the effect of nano-CMOS variability on asynchronous circuitsZheng Xie, Doug A. Edwards. 161-166 [doi]
- Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effectsTetsuya Iizuka, Toru Nakura, Kunihiro Asada. 167-172 [doi]
- Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAsMartin Straka, Jan Kastil, Zdenek Kotásek. 173-176 [doi]
- Testing analog electronic circuits using N-terminal networkPiotr Kyziol, Jerzy Rutkowski, Damian Grzechca. 177-180 [doi]
- The novel approach to wideband RFIC receivers in standard CMOS processLibor Majer, Viera Stopjaková. 181-184 [doi]
- A low phase noise 20 GHz voltage control oscillator using 0.18-μm CMOS technologyC. M. Yang, Hsuan-Ling Kao, Y. C. Chang, M. T. Chen, H. M. Chang, C. H. Wu. 185-188 [doi]
- Tree-model based mapping for energy-efficient and low-latency Network-on-ChipBo Yang 0009, Thomas Canhao Xu, Tero Säntti, Juha Plosila. 189-192 [doi]
- SREEP: Shift Register Equivalents Enumeration and Synthesis Program for secure scan designKatsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, Hideo Tamamoto. 193-196 [doi]
- A synthesis method to propagate false path information from RTL to gate levelSatoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara. 197-200 [doi]
- How to reduce size of a signature-based diagnostic dictionary used for testing of connectionsTomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka. 201-204 [doi]
- Highly linear down-conversion mixer in 65nm CMOS for a high supply voltage of 2.5VKurt Schweiger, Horst Zimmermann. 205-208 [doi]
- A mixer-filter combination of a direct conversion receiver for DVB-H applications in 65nm CMOSHeimo Uhrmann, Lukas Dörrer, Franz Kuttner, Kurt Schweiger, Horst Zimmermann. 209-212 [doi]
- A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologiesJacek Gradzki, Tomasz Borejko, Witold A. Pleskacz. 213-216 [doi]
- Intelligent IGBT driver concept for three-phase electric drive diagnosticsBohumil Klima, Jan Knobloch, Martin Pochyla. 217-220 [doi]
- Theorem proving techniques for the formal verification of NoC communications with non-minimal adaptive routingAmr Helmy, Laurence Pierre, Axel Jantsch. 221-224 [doi]
- CL: A flexible common language for processor hardware descriptionWenbiao Zhou, Per Karlström, Dake Liu. 225-228 [doi]
- Modeling temperature distribution in Networks-on-Chip using RC-circuitsAndreas Tockhorn, Claas Cornelius, Hagen Sämrow, Dirk Timmermann. 229-232 [doi]
- Enhancing pipelined processor architectures with fast autonomous recovery of transient faultsMarcus Jeitler, Jakob Lechner, Andreas Steininger. 233-236 [doi]
- Instruction set extensions for multi-threading in LEON3Martin Danek, Leos Kafka, Lukas Kohout, Jaroslav Sykora. 237-242 [doi]
- Wrapper design for a CDMA bus in SOCTatjana Nikolic, Mile K. Stojcev, Zoran Stamenkovic. 243-248 [doi]
- Evaluation of Radix-2 and Radix-4 FFT processing on a reconfigurable platformWaqar Hussain, Fabio Garzia, Jari Nurmi. 249-254 [doi]
- Cumulative embedded memory failure bitmap display & analysisNicola Campanelli, Tamas Kerekes, Paolo Bernardi, Mauricio de Carvalho, Alessandro Panariti, Matteo Sonza Reorda, Davide Appello, Mario Barone. 255-260 [doi]
- Using a CISC microcontroller to test embedded memoriesA. J. van de Goor, Said Hamdioui, Georgi Gaydadjiev. 261-266 [doi]
- Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOSSnorre Aunet, Amir Hasanbegovic. 267-272 [doi]
- Evaluation of transition untestable faults using a multi-cycle capture test generation methodMasayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki. 273-276 [doi]
- On analysis of fabricated polymorphic circuitsVaclav Simek, Richard Ruzicka, Lukás Sekanina. 281-284 [doi]
- A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loopKuo-Hsing Cheng, Chang-Chien Hu, Jen-Chieh Liu, Hong-Yi Huang. 285-288 [doi]
- A hardware accelerated framework for the generation of design validation programs for SMT processorsDanilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda. 289-292 [doi]
- Non-disjoint decomposition of logic functions in Reed-Muller spectral domainEdward Hrynkiewicz, Stefan Kolodzinski. 293-296 [doi]
- Memory optimizations for packet classification algorithms in FPGAViktor Pus, Juraj Blaho, Jan Korenek. 297-300 [doi]
- A 0.4 V bulk-input pseudo amplifier in 90nm CMOS technologyArash Ahmadpour. 301-304 [doi]
- A novel SRAM-based FPGA architecture for defect and fault tolerance of configurable logic blocksFarid Lahrach, Abderrazek Abdaoui, Abderrahim Doumar, Eric Châtelet. 305-308 [doi]
- Simulation-based sensitivity and worst-case analyses of automotive electronicsMonica Rafaila, Christian Decker, Christoph Grimm, Georg Pelz. 309-312 [doi]
- Synthesizing simulators for model checking microcontroller binary codeDominique Gückel, Bastian Schlich, Jörg Brauer, Stefan Kowalewski. 313-316 [doi]
- A deterministic approach for hardware fault injection in asynchronous QDI logicWerner Friesenbichler, Thomas Panhofer, Andreas Steininger. 317-322 [doi]
- Test pattern generation for the combinational representation of asynchronous circuitsRoland Dobai, Elena Gramatová. 323-328 [doi]
- Synthesis of asynchronous monitors for critical electronic systemsAlexandre Porcher, Katell Morin-Allory, Laurent Fesquet. 329-334 [doi]
- Synthesizing multiplier in reversible logicSebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler. 335-340 [doi]
- Window optimization of reversible and quantum circuitsMathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler. 341-345 [doi]
- On logic synthesis of conventionally hard to synthesize circuits using genetic programmingPetr Fiser, Jan Schmidt, Zdenek Vasícek, Lukás Sekanina. 346-351 [doi]
- Constraint-based test pattern generation at the Register-Transfer LevelTaavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko. 352-357 [doi]
- Fault diagnosis of crosstalk induced glitches and delay faultsShehzad Hasan, Ajoy Kumar Palit, Walter Anheier. 358-363 [doi]
- Reduction of power dissipation through parallel optimization of test vector and scan register sequencesZdenek Kotásek, Jaroslav Skarvada, Josef Strnadel. 364-369 [doi]
- Comparison of jitter decomposition methods for BER analysis of high-speed serial linksStefan Erb, Wolfgang Pribyl. 370-375 [doi]
- Analysis of power consumption and transition fault coverage for LOS and LOC testing schemesFangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen. 376-381 [doi]
- Low-cost, customized and flexible SRAM MBIST engineA. J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev. 382-387 [doi]
- Decoupling capacitance study and optimization method for high-performance VLSIsQing K. Zhu, Joe Yong, Tom Mozdzen. 388-392 [doi]
- Versatile sub-bandgap reference IP coreTomás Urban, Ondrej Subrt, Pravoslav Martínek. 393-398 [doi]
- A 12-bit fully differential 2MS/s successive approximation analog-to-digital converter with reduced power consumptionMilos Davidovic, Gerald Zach, Horst Zimmermann. 399-402 [doi]
- Receiver synchronization in video streaming with short latency over asynchronous networksJiri Halak, Sven Ubik, Petr Zejdl. 403-405 [doi]