Abstract is missing.
- A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline DelaysPeter Koo, Fabrizio Lombardi, Donatella Sciuto. 2-5
- Topological Routing Using Geometric InformationShinichiro Haruyama, D. F. Wong, Donald S. Fussell. 6-9
- An Optimal Channel Pin Assignment AlgorithmYang Cai, D. F. Wong. 10-13
- Constraint Identification for Timing VerificationJoel Grodstein, Jengwei Pan, William J. Grundmann, Bruce Gieseke, Yao-Tsung Yen. 16-19
- Race Detection for Two-Phase SystemsJoel Grodstein, Jim Montanaro, Susanne Marino. 20-23
- Timing Constraints for Correct PerformanceHabib Youssef, Eugene Shragowitz. 24-27
- An Automata-Theoretic Approach to Behavioral EquivalenceSrinivas Devadas, Kurt Keutzer. 30-33
- Tautology Checking Using Cross-Controllability and Cross-Observability RelationsEduard Cerny, C. Mauras. 34-37
- Automatic and Semi-Automatic Verification of Switch-Level Circuits with Temporal Logic and Binary Decision DiagramsMasahiro Fujita, Yusuke Matsunaga, Takeo Kakuda. 38-41
- A New Global Router Based on a Flow Model and Linear AssignmentG. Meixner, Ulrich Lauther. 44-47
- Rubber Band Routing and Dynamic Data RepresentationWayne Wei-Ming Dai, Raymond Kong, Jeffrey Jue. 52-55
- Touch and Cross RouterKaoru Kawamura, T. Shindo, Toshiyuki Shibuya, H. Miwatari, Y. Ohki. 56-59
- Exploitation of Periodicity in Logic Simulation of Synchronous CircuitsRahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich. 62-65
- SNEL: A Switch-Level Simulator Using Multiple Levels of Functional AbstractionDavid Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham. 66-69
- Optimization of the Parallel Technique for Compiled Unit-Delay SimulationPeter M. Maurer. 70-73
- Fast Switch-Level Fault Simulation Using Functional Fault ModelingE. Vandris, Gerald E. Sobelman. 74-77
- An Algorithm for Nearly-Minimal Collapsing of Finite-State Machine NetworksWayne Wolf. 80-83
- Implicit State Transition Graphs: Applications to Sequential Logic Synthesis and TestPranav Ashar, Abhijit Ghosh, Srinivas Devadas, A. Richard Newton. 84-87
- Minimization of Symbolic RelationsBill Lin, Fabio Somenzi. 88-91
- Algorithms for Discrete Function ManipulationArvind Srinivasan, Timothy Kam, Sharad Malik, Robert K. Brayton. 92-95
- Floorplanning with Pin AssignmentMassoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh. 98-101
- Diffusion - An Analytic Procedure Applied to Macro Cell PlacementChong-Min Kyung, Peter V. Kraus, Dieter A. Mlynski. 102-105
- Floorplanning by Topological Constraint ReductionGopalakrishnan Vijayan, Ren-Song Tsay. 106-109
- Design for Circuit Quality: Yield Maximization, Minimax, and Taguchi ApproachM. A. Styblinski. 112-115
- Computing Parametric Yield Accurately and EfficientlyLinda Milor, Alberto L. Sangiovanni-Vincentelli. 116-119
- Accurate and Efficient Evaluation of Circuit Yield and Yield GradientsPeter Feldmann, Stephen W. Director. 120-123
- A Unified Framework for the Formal Verification of Sequential CircuitsOlivier Coudert, Jean Christophe Madre. 126-129
- Implicit State Enumeration of Finite State Machines Using BDDsHervé J. Touati, Hamid Savoj, Bill Lin, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 130-133
- ATPG Aspects of FSM VerificationHyunwoo Cho, Gary D. Hachtel, Seh-Woong Jeong, Bernard Plessier, Eric M. Schwarz, Fabio Somenzi. 134-137
- FOLM-Planner: A New Floorplanner with a Frame Overlapping Floorplan Model Suitable for SOG (Sea-of-Gates) Type Gate ArraysMasako Murofushi, Masaaki Yamada, Takashi Mitsuhashi. 140-143
- Partitioning Algorithms for Layout Synthesis from Register-Transfer NetlistsAllen C.-H. Wu, Daniel Gajski. 144-147
- A Robust Framework for Hierarchical Floorplanning with Integrated Global WiringThomas Lengauer, Rolf Müller. 148-151
- GRCA: A Global Approach for Floorplanning Synthesis in VLSI Macrocell DesignAlexander Herrigel. 152-155
- Mixed-Mode Incremental Simulation and Concurrent Fault SimulationYun-Cheng Ju, Fred L. Yang, Resve A. Saleh. 158-161
- Incorporation of Inductors in Piecewise Approximate Circuit SimulationChandramouli Visweswariah, Peter Feldmann, Ronald A. Rohrer. 162-165
- Analysis of VLSI Microconductor Systems by Bi-Level Waveform RelaxationRui Wang, Omar Wing. 166-169
- Measuring Error Propagation in Waveform Relaxation AlgorithmsCharles A. Zukowski, George Gristede, Albert E. Ruehli. 170-173
- Extraction of Functional Information from Combinatorial CircuitsM. Ohmura, Hiroto Yasuura, Keikichi Tamaru. 176-179
- An O(::::n:::::::3:::log::::n::::)-Heuristic for Microcode Bit OptimizationSe-Kyoung Hong, In-Cheol Park, Chong-Min Kyung. 180-183
- Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic SpecificationsPeter Vanbekbergen, Francky Catthoor, Gert Goossens, Hugo De Man. 184-187
- High-Level Delay Estimation for Technology-Independent Logic EquationsDavid E. Wallace, Mandalagiri S. Chandrasekhar. 188-191
- A High-Packing Density Module Generator for Bipolar Analog LSIsYoichi Shiraishi, Mitsuyuki Kimura, Kazuhiko Kobayashi, Tetsuro Hino, Miki Seriuchi, Manabu Kusaoke. 194-197
- Constraint-Based Channel Routing for Analog and Mixed Analog/Digital CircuitsUmakanta Choudhury, Alberto L. Sangiovanni-Vincentelli. 198-201
- A Routing Methodology for Analog Integrated CircuitsEnrico Malavasi, Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli. 202-205
- The Component Sythesis Algorithm: Technology Mapping for Register Transfer DescriptionsElke A. Rundensteiner, Daniel Gajski, Lubomir Bic. 208-211
- MOSP: Module Selection for Pipelined Designs with Multi-Cycle OperationsRajiv Jain. 212-215
- Partitioning of Functional Models of Synchronous Digital SystemsRajesh K. Gupta, Giovanni De Micheli. 216-219
- Contest: A Fast ATPG Tool for Very Large Combinatorial CircuitsUdo Mahlstedt, Torsten Grüning, Cengiz Özcan, Wilfried Daehn. 222-225
- A Single-State-Transition Fault Model for Sequential MachinesKwang-Ting Cheng, Jing-Yang Jou. 226-229
- Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation AlgorithmChun-Hung Chen, Jacob A. Abraham. 230-233
- A Parallel Algorithm for Hierarchical Circuit ExtractionKrishna P. Belkhale, Prithviraj Banerjee. 236-239
- XREF/COUPLING: Capacitive Coupling Error CheckerWilliam J. Grundmann, Yao-Tsung Yen. 244-247
- Preform: A Process Independent Symbolic Layout SystemJean-Claude Dufourd, Jean-François Naviner, Francis Jutand. 248-251
- SALSA: A New Approach to Scheduling with Timing ConstraintsJohn A. Nestor, Ganesh Krishnamoorthy. 262-265
- A Hierarchical Approach for Testing Large CircuitsSusana Stoica. 268-271
- On the Efficiency of the Transition Fault Model for Delay FaultsManfred Geilert, Jürgen Alt, Michael Zimmermann. 272-275
- Evaluation and Synthesis of Self-Monitoring State MachinesScott H. Robinson, John Paul Shen. 276-279
- QUIETEST: A Quiescent Current Testing Methodology for Detecting Leakage FaultsWeiwei Mao, Ravi K. Gulati, Deepak K. Goel, Michael D. Ciletti. 280-283
- CADICS - Cyclic Analog-to-Digital Converter SynthesisGani Jusuf, Paul R. Gray, Alberto L. Sangiovanni-Vincentelli. 286-289
- A Usable Circuit Optimizer for DesignersDale E. Hocevar, Rajeev Arora, Uttiya Dasgupta, Sattam Dasgupta, Nagaraj Subramanyam, Sham Kashyap. 290-293
- Optimal Test Set Design for Analog CircuitsLinda Milor, Alberto L. Sangiovanni-Vincentelli. 294-297
- Feedback-Driven Datapath Optimization in FasoltDavid Knapp. 300-303
- Data Path Construction and RefinementFur-Shing Tsai, Yu-Chin Hsu. 308-311
- Partial Scan by Use of Empirical TestabilityKee Sup Kim, Charles R. Kime. 314-317
- On Determining Scan Flip-Flops in Partial-Scan DesignsDong-Ho Lee, Sudhakar M. Reddy. 322-325
- A Fast Algorithm for Performance-Driven PlacementMichael A. B. Jackson, Arvind Srinivasan, Ernest S. Kuh. 328-331
- Congestion-Driven Placement Using a New Multi-Partitioning HeuristicStefan Mayrhofer, Ulrich Lauther. 332-335
- New Algorithms for the Placement and Routing of Macro CellsWilliam Swartz, Carl Sechen. 336-339
- VLSI Placement Using Uncertain CostsCheryl Harkness, Daniel P. Lopresti. 340-343
- Knowledge Based Design Flow ManagementFelix Bretschneider, Christa Kopf, Helmut Lagger, Arding Hsu, Elizabeth Wei. 350-353
- A CAD Process Scheduling TechniqueToshiaki Miyazaki, Tamio Hoshino, Makoto Endo. 354-357
- A History Model for Managing the VLSI Design ProcessTzi-cker Chiueh, Randy H. Katz. 358-361
- On the Diagnostic Resolution of Signature AnalysisJanusz Rajski, Jerzy Tyszer, Babak Salimi. 364-367
- Computing the Error Escape Probability in Count-Based Compaction SchemesAndré Ivanov, Yervant Zorian. 368-371
- Partial Detectability ProfilesPaul G. Ryan, W. Kent Fuchs. 372-375
- A Routing System for Mixed A/D Standard Cell LSIsIkuo Harada, Hitoshi Kitazawa, Takao Kaneko. 378-381
- A Detailed Router for Field-Programmable Gate ArraysStephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic. 382-385
- Three-Dimensional Routing for Multilayer Ceramic Printed Circuit BoardsAkihiko Hanafusa, Yasuhiro Yamashita, Mitsuru Yasuda. 386-389
- Simulating Electromagnetic Radiation of Printed Circuit BoardsHansruedi Heeb, Albert E. Ruehli, J. Janak, Shahrokh Daijavad. 392-395
- An Integrated Hot-Carrier Degradation Simulator for VLSI Reliability AnalysisYusuf Leblebici, Sung-Mo Kang. 400-403
- Multi-Level Logic Minimization Across Latch BoundariesYusuke Matsunaga, Masahiro Fujita, Takeo Kakuda. 406-409
- Performance Optimization of Pipelined CircuitsSharad Malik, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 410-413
- Don t Care Minimization of Multi-Level Sequential Logic NetworksBill Lin, Hervé J. Touati, A. Richard Newton. 414-417
- A Clock Net Reassignment Algorithm Usign Voronoi DiagramMasato Edahiro. 420-423
- An Exact Algorithm for Single-Layer Wire-Length MinimizationJan-Ming Ho, Majid Sarrafzadeh, Atsushi Suzuki. 424-427
- A New Class of Steiner Trees Heuristics with Good Performance: The Iterated 1-Steiner-ApproachAndrew B. Kahng, Gabriel Robins. 428-431
- Rectilinear Steiner Tree Construction by Local and Global RefinementTing-Hai Chao, Yu-Chin Hsu. 432-435
- Circuit Simulation Algorithms on a Distributed Memory Multiprocessor SystemJohn A. Trotter, Prathima Agrawal. 438-441
- Parallel Simulation Algorithms for Grid-Based Analog Signal ProcessorsLuis Miguel Silveira, Andrew Lumsdaine, Jacob White. 442-445
- A Parallel Block-Diagonal Preconditioned Conjugate-Gradient Solution Algorithm for Circuit and Device SimulationsKartikeya Mayaram, Ping Yang, Jue-Hsien Chern, Richard Burch, Lawrence A. Arledge Jr., Paul F. Cox. 446-449
- Fast Overlapped Scattered Array Storage Schemes for Sparse MatricesJohn A. Trotter, Prathima Agrawal. 450-453
- Testability-Preserving Circuit TransformationsMichael J. Bryan, Srinivas Devadas, Kurt Keutzer. 456-459
- Timing Optimization with Testability ConsiderationsAlexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng. 460-463
- Efficient Automatic Diagnosis of Digital CircuitsHeh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin. 464-467
- An Algorithm for Locating Logic Design ErrorsMasahiro Tomita, Hong-Hai Jiang, Tamotsu Yamamoto, Yoshihiro Hayashi. 468-471
- Logic Compilation from Graphical Dependency NotationJukka Lahti, Jorma Kivelä. 474-477
- HS: A Hierarchical Search Package for CAD DataNishit P. Parikh, Chi-Yuan Lo, Anoop Singhal, Kwok W. Wu. 478-481
- A Data Flow Based Architecture for CAD FrameworksPeter van den Hamer, Menno Treffers. 482-485
- An Algebra for Switch-Level SimulationIbrahim N. Hajj. 488-491
- A New Method for Assigning Signal Flow Directions to MOS TransistorsKuen-Jong Lee, Rajiv Gupta, Melvin A. Breuer. 492-495
- Logic Simulation and Parallel ProcessingVishwani D. Agrawal, Srimat T. Chakradhar. 496-499
- Observability Don t Care Sets and Boolean RelationsMaurizio Damiani, Giovanni De Micheli. 502-505
- PHIFACT, a Boolean Preprocessor for Multi-Level Logic SynthesisF. Crowet, Marc Davio, C. Dierieck, J. Durieu, G. Louis, Chantal Ykman-Couvreur. 506-509
- A Method for Concurrent Decomposition and Factorization of Boolean ExpressionsJagadeesh Vasudevamurthy, Janusz Rajski. 510-513
- A Two-Level Two-Way Partitioning AlgorithmYen-Chuen Wei, Chung-Kuan Cheng. 516-519
- Finding Clusters in VLSI CircuitsJörn Garbers, Hans Jürgen Prömel, Angelika Steger. 520-523
- AWEsim: A Program for the Efficient Analysis of Linear(ized) CircuitsXiaoli Huang, Vivek Raghavan, Ronald A. Rohrer. 534-537
- Efficient Pole Zero Sensitivity Calculation in AWEJohn Y. Lee, Xiaoli Huang, Ronald A. Rohrer. 538-541
- Analysis of High-Speed VLSI Interconnects Using the Asymptotic Waveform Evaluation TechniqueTak K. Tang, Michel S. Nakhla. 542-545
- DC Parameterized Piecewise-Function Transistor Models for Bipolar and MOS Logic Stage Delay EvaluationDouglas R. Holberg, Santanu Dutta, Lawrence T. Pillage. 546-549
- ::::check:::: T::c:: and ::::min:::: T::c::: Timing Verification and Optimal Clocking of Synchronous Digtal CircuitsKarem A. Sakallah, Trevor N. Mudge, Kunle Olukotun. 552-555
- A Framework Environment for Logic Design Support SystemKaname Kuroki, Nobuyoshi Nomizu, Shigenobu Suzuki, Kazutoshi Takahashi. 556-559
- MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued InputsLuciano Lavagno, Sharad Malik, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 560-563