Abstract is missing.
- Gigachip Technology and the Signal Processing RevolutionPallab K. Chatterjee. 4
- Application of High-Level Synthesis in an Industrial ProjectAhmed Hemani, Börje Karlsson, Mats Fredriksson, Kurt Nordqvist, Björn Fjellborg. 5-10
- An Empirical Study on the Effects of Physical Design in High-Level SynthesisPradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi. 11-16
- ILP-Based Scheduling with Time and Resource Constraints in High Level SynthesisSamit Chaudhuri, Robert A. Walker. 17-20
- FAST: FPGA Targeted RTL Structure Synthesis TechniqueA. R. Naseer, M. Balakrishnan, Anshul Kumar. 21-24
- Ultra Fine-Grain Template-Driven SynthesisDavid J. Kolson, Nikil D. Dutt, Alexandru Nicolau. 25-28
- Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD MachineSharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester. 29-32
- SEMU: A Parallel Processing System for Timing Simulation of Digital CMOS VLSI CircuitsAbhaya Asthana, Mike Laznovsky, Boyd Mathews. 33-38
- CM-SIM: A Parallel Circuit Simulator on a Distributed Memory MultiprocessorC. V. Ramamoorthy, Vikram Vij. 39-44
- Parallel Model Evaluation for Circuit Simulation on the PACE MultiprocessorPrathima Agrawal, Sanjay Goil, Sally Liu, John A. Trotter. 45-48
- Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility GraphsDharmavani Bhagavathi, Stephan Olariu, James L. Schwing, Jingyuan Zhang. 49-52
- Analog Modeling Using Event-Driven HDL sDundar Dumlugol, Don Webber, Rajeev Madhavan. 53-56
- A SPICE Model of RLGC Transmission Line with Error ControlQingjian Yu, Omar Wing. 57-60
- Multiple Fault Testing in Analog CircuitsNaim Ben Hamida, Bozena Kaminska. 61-66
- The Design of Analog Self-Checking CircuitsBapiraju Vinnakota, Ramesh Harjani. 67-70
- OTA Based Neural Network Architectures with On-Chip Tuning of SynapsesJoydeep Ghosh, Patrick LaCour, Spence Jackson. 71-76
- TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 CompressorDebabrata Ghosh, S. K. Nandy, K. Parthasarathy. 77-82
- Calculation of Minimum Number of Registers in Arbitrary Life Time ChartKeshab K. Parhi. 83-86
- A Fast Algorithm for Performing Vector Quantization and its VLSI ImplementationHeonchul Park, Viktor K. Prasanna. 91-94
- A 600MHz Half-Bit Level Pipelined Multiplier MacrocellDebabrata Ghosh, Shamik Sural, S. K. Nandy. 95-100
- A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow GraphShang-E Tai, Debashis Bhattacharya. 101-106
- Simulated Annealing for Target-Oriented ScanC. P. Ravikumar, H. Rasheed. 107-112
- A Bist PLA Design for High Fault Coverage and Testing by an Interleavingly Crosspoint CountingMd. Abdul Mottalib, P. Dasgupta. 117-122
- Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault ModelHarry Hengster, Rolf Drechsler, Bernd Becker. 123-126
- Flipping Modules to Improve Circuit Performance and RoutabilityKeumog Ahn, Sartaj Sahni. 127-132
- A New Genetic Algorithm for the Channel Routing ProblemJens Lienig, Krishnaiyan Thulasiraman. 133-136
- High Performance Over-the-Cell RoutingJim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani. 137-142
- Over-the-Cell Routing Algorithms for Industrial Cell ModelsSiddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani. 143-148
- Two-Layer Wiring with Pin Preassignments is Easier if the Power Supply Nets are Already GeneratedPaul Molitor, Uwe Sparmann, Dorothea Wagner. 149-154
- Rapid Technology Projection for High-Level SynthesisPradip K. Jha, Nikil D. Dutt. 155-158
- Behavioral Design and Prototyping of a Fail-Safe SystemYinghua Min, Yutang Zhou, Zhongcheng Li, Cheng Ye, Yuqi Pan. 159-162
- BINET: An Algorithm for Solving the Binding ProblemAshutosh Majumdar, Minjoong Rim, Rajiv Jain, Renato De Leone. 163-168
- A CAD Tool for Design of On-Chip Store & Generate SchemeS. Nandi, Vamsi Boppana, Parimal Pal Chaudhuri. 169-174
- HSIM1 and HSIM2: Object Oriented Algorithms for VHDL SimulationNeeta Ganguly, Vijay Pitchumani. 175-178
- ::::I::DDQ:::::: Measurement Based Diagnosis of Bridging Faults in Full Scan CircuitsSreejit Chakravarty, Sivaprakasam Suresh. 179-182
- ::::I::DDQ:::::: Detection of CMOS Bridging Faults by Stuck-At Fault TestsS. Hwang, Rochit Rajsuman, Scott Davidson. 183-186
- The Effect of Built-In Current Sensors (BICS) on Operational and Test PerformanceSankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong. 187-190
- On Testability of Differential Split-Level CMOS CircuitsS. M. Aziz, W. A. J. Waller. 191-196
- Testable Realizations of CMOS Combinatorial Circuits for Voltage and Current TestingK. Biswas, S. Rai. 197-202
- On the Synthesis of Gate Matrix LayoutReena Agarwal, Indranil Sengupta. 203-206
- SAGA: A Unification of the Genetic Algorithm with Simulated Annealing and its Application to Macro-Cell PlacementHenrik Esbensen, Pinaki Mazumder. 211-214
- GLOVE: A Graph-Based Layout VerifierCyrus Bamji, Jonathan Allen. 215-220
- A Sea-of-Gates Style FPGA Placement AlgorithmKalapi Roy-Neogi, Bingzhong Guan, Carl Sechen. 221-224
- A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAsG. N. Rathna, S. K. Nandy, K. Parthasarathy. 225-228
- High Speed Digital Filtering on SRAM-Based FPGAsA. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal. 229-232
- Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA ArchitecturesMahesh Mehendale. 233-236
- Detailed Routing of Multi-Terminal Nets in FPGAsAmit Chowdhary, Dinesh Bhatia. 237-242
- A Switch-Memory Chip for Packet Switching at Gigabits per SecondHemant Kanakia. 243-246
- Laout Influenced Factorization of Boolean FunctionsArunita Jaekel, Subir Bandyopadhyay, Abhijit Sengupta. 251-254
- On Determining Symmetries in Inputs of Logic CircuitsIrith Pomeranz, Sudhakar M. Reddy. 255-260
- Energy Efficient Programmable ComputationAnantha Chandrakasan, Mani B. Srivastava, Robert W. Brodersen. 261-264
- Synthesis of Low Power Linear DSP Circuits Using Activity MetricsAbhijit Chatterjee, Rabindra K. Roy. 265-270
- Power Constraint Scheduling of TestsRichard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal. 271-274
- Design of an Application Specific VLSI Chip for Image RotationIndradeep Ghosh, Bandana Majumdar. 275-278
- Architecture for VLSI Design of CA Based Byte Error Correcting Code DecodersDipanwita Roy Chowdhury, Parimal Pal Chaudhuri. 283-286
- VLSI Architecture for HDTV Motion Estimation Based on Block-Matching AlgorithmFeng-Ming Yang, Stefan Wolter, Rainer Laur. 287-290
- ACE: A VLSI Chip for Galois Field GF (2:::m:::) Based ExponentiationMario Kovac, N. Ranganathan. 291-296
- An Optimal Design for Parallel Test Generation Based on Circuit PartitioningDong Xiang, Dao-zheng Wei. 297-300
- Data Path Testability Evaluation via Functional Testability MeasuresMohamed Jamoussi, Bozena Kaminska. 301-306
- An Improved Deductive Fault SimulatorP. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal. 307-310
- On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit DecompositionSunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi. 311-314
- Finite Element Analysis of SIGe npn HBTG. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee. 319-322
- ::::n::::OHM - A Multi-Process Device Synthesis Tool for Lateral DMOS StructuresSrikanth Natarajan, Debapriya Sahu, Sattam Dasgupta. 323-327
- 3D Effects in VLSI/ULSI MOSFETs: A Novel Analytical Approach to Model Threshold VoltageShuvendu K. Lahiri, M. K. Das, A. Das Gupta, I. Manna. 328-332
- LATCHSIM - A Lath-Up Simulator in VLSI CAD Environment for CMOS and BiCMOS CircuitsA. Bandyopadhyay, P. R. Verma, A. B. Bhattacharyya, M. J. Zarabi. 339-342
- Hierarchical Reconfiguration of VLSI/WSI ArraysDinesh Bhatia, Ramesh Rajagopalan, Srinivas Katkoori. 349-352
- A Linear Systolic Array for LU DecompositionEmmanuel Casseau, Dominique Degrugillier. 353-358
- An Algorithm to Test Reconfigured RAMsManoj Franklin, Kewal K. Saluja. 359-364
- Response Pipelined CAM Chips: The First Generation and BeyondKanad Ghose, V. Anand Dharmaraj. 365-368
- An Integrated Approach to State Assignment and Sequential Element Selection for FSM SynthesisMahesh Mehendale, Biswadip Mitra. 369-372
- A New Approach to Synthesis of PLA-Based FSM sChunduri Rama Mohan, Partha Pratim Chakrabarti. 373-378
- Bitwise Encoding of Finite State MachinesJosé C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto. 379-382
- Synthesis of Initializable Asynchronous CircuitsSrimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan. 383-388
- Mechanical Identification of Inductive Properties During Verification of Finite State MachinesI. Chakrabarti, Dilip Sarkar. 389-394
- Graphical Methodology Language for CAD FrameworksJames Sienicki, Michael L. Bushnell, Sandip Parikh. 401-406
- An Object Oriented Environment for Modeling and Synthesis of Hardware CircuitsSantonu Sarkar, Anupam Basu. 407-412
- Early Exploration of the Multi-Dimensional VLSI Design SpaceMourad B. Takla, Donald W. Bouldin, Daniel B. Koch. 413-416
- Verification of Circuits Described in VHDL through Extraction of Design IntentYatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell. 417-420