| 7 | -- | 15 | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey. Power management in high-level synthesis |
| 16 | -- | 24 | Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De. Design and optimization of dual-threshold circuits for low-voltage low-power applications |
| 25 | -- | 29 | J. Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, T. F. Chen. Segmented bus design for low-power systems |
| 30 | -- | 37 | Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand. Peephole optimization of asynchronous macromodule networks |
| 38 | -- | 47 | Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems. The spring scheduling coprocessor: a scheduling accelerator |
| 48 | -- | 55 | Tong Liu, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi. Test generation and scheduling for layout-based detection of bridge faults in interconnects |
| 56 | -- | 68 | Gauthier Lafruit, Francky Catthoor, Jan Cornelis, Hugo De Man. An efficient VLSI architecture for 2-D wavelet image coding with novel image scan |
| 69 | -- | 79 | George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar. Multilevel hypergraph partitioning: applications in VLSI domain |
| 80 | -- | 91 | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic. The memory/logic interface in FPGAs with large embedded memory arrays |
| 92 | -- | 104 | Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha. COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems |
| 105 | -- | 110 | Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini. An efficient VLSI architecture for real-time additive synthesis of musical signals |
| 111 | -- | 115 | Victor V. Zyuban, Peter M. Kogge. Application of STD to latch-power estimation |
| 116 | -- | 120 | Wang-Dauh Tseng, Kuochen Wang. Fuzzy-based CMOS circuit partitioning in built-in current testing |
| 121 | -- | 124 | Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds. High performance low power array multiplier using temporal tiling |
| 125 | -- | 129 | Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan. Computation of lower bounds for switching activity using decision theory |
| 130 | -- | 134 | C. Y. Wang, K. Roy. An activity-driven encoding scheme for power optimization in microprogrammed control unit |
| 135 | -- | 138 | Rong Lin, Stephan Olariu. Efficient VLSI architectures for Columnsort |
| 139 | -- | 144 | Hiroyuki Mizuno, Koichiro Ishibashi. A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio |
| 144 | -- | 148 | F. Mu, C. Svensson. A layout-based schematic method for very high-speed CMOS cell design |