Fuminori Kobayashi - researchr alias

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Viewing Publication 1 - 35 from 35

2022

Analog Correlator by a Dynamically-Reconfigured Switched-Capacitor CircuitFuminori Kobayashi. iscas 2022: 663-666 [doi]

2016

Direct optical communication on an optically reconfigurable gate arrayShinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi. fgct 2016: 17-20 [doi]

2015

Integrally accurate resolver-to-digital converter (RDC)Nordinah Ismail, Fuminori Kobayashi, Manabu Inoue. ascc 2015: 1-4 [doi]

2011

Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memoryTakayuki Mabuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi. ahs 2011: 44-49 [doi]

2010

A motor speed control system using a hybrid of dual-loop PLL and feed-forwardHidekazu Machida, Michinobu Kambara, Kouta Tanaka, Fuminori Kobayashi. amc 2010: 185-190 [doi]

2009

A PLL configuration for reducing both incoming and inherent jittersFuminori Kobayashi, Yuhta Egashira, Hitoshi Kondoh. icecsys 2009: 93-96 [doi]

2008

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 PerspectiveFuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe. ersa 2008: 222-228

Low-jitter PLL by interpolate compensationYutaka Nakanishi, Fuminori Kobayashi, Hitoshi Kondoh. apccas 2008: 1078-1081 [doi]

2007

A multi-context holographic memory recording system for Optically Reconfigurable Gate ArraysRio Miyazaki, Minoru Watanabe, Fuminori Kobayashi. ipps 2007: 1-7 [doi]

Holographic memory reconfigurable VLSIMinoru Watanabe, Fuminori Kobayashi. iscas 2007: 401-404 [doi]

272 Gate Count Optically Differential Reconfigurable Gate Array VLSIMinoru Watanabe, Takenori Shiki, Fuminori Kobayashi. ersa 2007: 259-264

2006

A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic MemoryMinoru Watanabe, Fuminori Kobayashi. fpl 2006: 1-6 [doi]

An optically differential reconfigurable gate array with a holographic memoryMinoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi. ipps 2006: [doi]

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate ArrayMinoru Watanabe, Fuminori Kobayashi. ersa 2006: 239-240

Power consumption advantage of a dynamic optically reconfigurable gate arrayMinoru Watanabe, Fuminori Kobayashi. ipps 2006: [doi]

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technologyMinoru Watanabe, Fuminori Kobayashi. aspdac 2006: 108-109 [doi]

Differential Reconfiguration Architecture suitable for a Holographic MemoryMinoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi. ersa 2006: 198-206

A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIMinoru Watanabe, Fuminori Kobayashi. arc 2006: 268-273 [doi]

Logic Synthesis and Place-and-Route Environment for ORGAsMinoru Watanabe, Fuminori Kobayashi. ersa 2006: 237-238

2005

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELsMototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi. isvlsi 2005: 274-275 [doi]

Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse LasersMototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi. fpt 2005: 287-288

An Improved Dynamic Optically Reconfigurable Gate ArrayMinoru Watanabe, Fuminori Kobayashi. isvlsi 2005: 136-141 [doi]

An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration CircuitMinoru Watanabe, Fuminori Kobayashi. ipps 2005: [doi]

A Zero-Overhead Dynamic Optically Reconfigurable Gate ArrayMinoru Watanabe, Fuminori Kobayashi. fpt 2005: 297-298

A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technologyMinoru Watanabe, Fuminori Kobayashi. iscas 2005: 1214-1217 [doi]

2004

2003

An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration CircuitMinoru Watanabe, Fuminori Kobayashi. ipps 2003: 188 [doi]

2002

An optically differential reconfigurable gate array and its power consumption estimationMinoru Watanabe, Fuminori Kobayashi. fpt 2002: 197-202 [doi]

1996

Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)Fuminori Kobayashi, Masayuki Haratsu, Masateru Yabumoto, Michio Nakano. tie, 43(6):616-620, 1996. [doi]

1995

A Digital PLL with Finite Impulse ResponsesFuminori Kobayashi, Masayuki Haratsu. iscas 1995: 191-194

1987

Time-varying signals analysis using squared analytic signalsFuminori Kobayashi, Hiroshi Suzuki. icassp 1987: 1525-1528 [doi]

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