Rainer G. Spallek - researchr alias

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2011

Accelerating Computations on FPGA Carry Chains by Operand CompactionThomas B. Preußer, Martin Zabel, Rainer G. Spallek. arith 2011: 95-102 [doi]

2010

2009

Generating the trace qualification configuration for MCDS from a high level languageJens Braunes, Rainer G. Spallek. date 2009: 1560-1563 [doi]

Mapping basic prefix computations to fast carry-chain structuresThomas B. Preußer, Rainer G. Spallek. fpl 2009: 604-608 [doi]

2008

Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, ProceedingsUwe Brinkschulte, Theo Ungerer, Christian Hochberger, Rainer G. Spallek, editors, Volume 4934 of Lecture Notes in Computer Science, Springer, 2008.

Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case StudySteffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek. arc 2008: 296-301 [doi]

2007

2006

A Compiler-Oriented Architecture Description for Reconfigurable SystemsJens Braunes, Rainer G. Spallek. arc 2006: 443-448 [doi]

Prototyping and Application Development Framework for Dynamically Reconfigurable DSP ArchitecturesSteffen Köhler, Martin Zimmerling, Martin Zabel, Rainer G. Spallek. arcs 2006: 142-151

Analysis of a Fully-Scalable Digital Fractional Clock DividerThomas B. Preuber, Rainer G. Spallek. asap 2006: 173-177 [doi]

2005

Ein Zwischenformat-Profiler für das RECAST-FrameworkJens Braunes, Steffen Köhler, Annett Königsmann, Rainer G. Spallek. arcs 2005: 33-38

2004

RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable ArchitecturesJens Braunes, Steffen Köhler, Rainer G. Spallek. arcs 2004: 156-166 [doi]

Increasing ILP of RISC Microprocessors Through Control-Flow Based ReconfigurationSteffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek. fpl 2004: 781-790 [doi]

RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded ComputingThomas Preußer, Steffen Köhler, Rainer G. Spallek. csreaESA 2004: 130-135

2003

Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable PlatformsSergej Sawitzki, Rainer G. Spallek. fpl 2003: 1119-1122 [doi]

2002

A Reconfigurable System-on-Chip-Based Fast EDM Process MonitorSebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz. fpl 2002: 1164-1167 [doi]

Improving Code Efficiency for Reconfigurable VLIW ProcessorsSteffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek. ipps 2002: [doi]

2001

Prototyping Framework for Reconfigurable ProcessorsSergej Sawitzki, Steffen Köhler, Rainer G. Spallek. fpl 2001: 6-16 [doi]

2000

Formal Verification of a Reconfigurable MicroprocessorSergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube. fpl 2000: 781-784 [doi]

Formal Verification for Microprocessors with Extendable Instruction SetSergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube. asap 2000: 47-55 [doi]

1999

Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable LogicSteffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek. ipps 1999: 706-708

A Concept for an Evaluation Framework for Reconfigurable SystemsSergej Sawitzki, Rainer G. Spallek. fpl 1999: 475-480

1998

Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten UmgebungenRaimar Falke, Michael Peter, Achim Gratz, Rainer G. Spallek. jit 1998: 354-363

Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic ArraysSergej Sawitzki, Achim Gratz, Rainer G. Spallek. fpl 1998: 411-415 [doi]

1997

Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen PlattformenAchim Gratz, Rainer G. Spallek. mmb 1997: 51-58

A RISC Processor with Extended ForwardingGert Markwardt, Günter Kemnitz, Rainer G. Spallek. arcs 1997: 163-169