Abstract is missing.
- Efficient Simulation of Structural Faults for the Reliability Evaluation at System-LevelMichael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto. 3-8 [doi]
- Jitter Characterization of Pseudo-random Bit Sequences Using Incoherent Sub-samplingHyun Choi, Abhijit Chatterjee. 9-14 [doi]
- FSimGP^2: An Efficient Fault Simulator with GPGPUMin Li, Michael S. Hsiao. 15-20 [doi]
- A Quasi-best Random TestingShiyi Xu, Peng Xu. 21-26 [doi]
- Testing of Low-Cost Digital Microfluidic Biochips with Non-regular Array LayoutsYang Zhao, Krishnendu Chakrabarty. 27-32 [doi]
- Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible CircuitsDipak K. Kole, Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya. 33-38 [doi]
- On Determining the Real Output Xs by SAT-Based ReasoningMelanie Elm, Michael A. Kochte, Hans-Joachim Wunderlich. 39-44 [doi]
- On Selection of Testable Paths with Specified Lengths for Faster-Than-At-Speed TestingXiang Fu, Huawei Li, Xiaowei Li. 45-48 [doi]
- Test Pattern Selection and Compaction for Sequential Circuits in an HDL EnvironmentM. H. Haghbayan, S. Karamati, F. Javaheri, Zainalabedin Navabi. 53-56 [doi]
- Tackling the Path Explosion Problem in Symbolic Execution-Driven Test Generation for ProgramsSaparya Krishnamoorthy, Michael S. Hsiao, Loganathan Lingappan. 59-64 [doi]
- A Reliability Model for Object-Oriented SoftwarePeng Xu, Shiyi Xu. 65-70 [doi]
- A New Approach to Generating High Quality Test CasesPan Liu, Huaikou Miao. 71-76 [doi]
- A Study on Software Reliability Prediction Based on Transduction InferenceJungang Lou, Jianhui Jiang, Chunyan Shuai, Ying Wu. 77-80 [doi]
- Formula-Oriented Compositional Minimization in Model CheckingBowen Chen, Haihua Shen, Wenhui Zhang. 81-84 [doi]
- Variation-Aware Fault ModelingFabian Hopsch, Bernd Becker, Sybille Hellebrand, Ilia Polian, Bernd Straube, Wolfgang Vermeiren, Hans-Joachim Wunderlich. 87-93 [doi]
- Diagnosis of Multiple Physical Defects Using Logic Fault ModelsXun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy. 94-99 [doi]
- A Memory Fault Simulator for Radiation-Induced Effects in SRAMsPaolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo. 100-105 [doi]
- On Soft Error Immunity of Sequential CircuitsDan Zhu, Tun Li, Sikun Li. 106-110 [doi]
- Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman ProblemDebasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. 111-116 [doi]
- P^(2)CLRAF: An Pre- and Post-Silicon Cooperated Circuit Lifetime Reliability Analysis FrameworkSong Jin, Yinhe Han, Huawei Li, Xiaowei Li. 117-120 [doi]
- A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory InterfacesHyunjin Kim, Jacob A. Abraham. 123-128 [doi]
- A Complete Logic BIST Technology with No Storage RequirementWei-Cheng Lien, Kuen-Jong Lee. 129-134 [doi]
- Built-In Self-Test for Capacitive MEMS Using a Charge Control TechniqueIftekhar Ibne Basith, Nabeeh Kandalaft, Rashid Rashidzadeh. 135-140 [doi]
- Defect Coverage-Driven Window-Based Test CompressionXrysovalantis Kavousianos, Krishnendu Chakrabarty, Emmanouil Kalligeros, Vasileios Tenentes. 141-146 [doi]
- Controlling Peak Power Consumption for Scan Based Multiple Weighted Random BISTHiroshi Yokoyama, Hideo Tamamoto, Kewal K. Saluja. 147-152 [doi]
- Parallel LFSR Reseeding with Selection Register for Mixed-Mode BISTPiyanart Kongtim, Taweesak Reungpeerakul. 153-158 [doi]
- Efficient Embedding of Deterministic Test DataMudassar Majeed, Daniel Ahlstrom, Urban Ingelsson, Gunnar Carlsson, Erik Larsson. 159-162 [doi]
- Test Data Reduction for BIST-Aided Scan Test Using Compatible Flip-Flops and Shifting Inverter CodeMasashi Ishikawa, Hiroyuki Yotsuyanagi, Masaki Hashizume. 163-166 [doi]
- On-chip Jitter Measurement Using Vernier Ring Time-to-Digital ConverterJianjun Yu, Fa Foster Dai. 167-170 [doi]
- Pattern Encodability Enhancements for Test Stimulus DecompressorsNader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla. 173-178 [doi]
- High Performance Compaction for Test Responses with Many UnknownsThomas Rabenalt, Michael Richter, Michael Gössel. 179-184 [doi]
- Design-for-Test of Digitally-Assisted Analog IPs for Automotive SoCsYizi Xing, Liquan Fang. 185-191 [doi]
- Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation MethodJing Ye, Xiaolin Zhang, Yu Hu, Xiaowei Li. 192-197 [doi]
- D-Scale: A Scalable System-Level Dependable Method for MPSoCsNicolas Hebert, Pascal Benoit, Gilles Sassatelli, Lionel Torres. 198-205 [doi]
- Bipartite Full Scan Design: A DFT Method for Asynchronous CircuitsHiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara. 206-211 [doi]
- XOR-Based Response Compactor Adaptive to X-Density VariationSamah Mohamed Saeed, Ozgur Sinanoglu. 212-217 [doi]
- DFT + DFD: An Integrated Method for Design for Testability and DiagnosabilityNikhil P. Rahagude, Maheshwar Chandrasekar, Michael S. Hsiao. 218-223 [doi]
- Accelerating Strategy for Functional Test of NoC Communication FabricYan Zheng, Hong Wang, Shiyuan Yang, Chen Jiang, Feiyu Gao. 224-227 [doi]
- HYPERA: High-Yield Performance-Efficient Redundancy AnalysisTsung-Chu Huang, Kuei-Yeh Lu, Yen-Chieh Huang. 231-236 [doi]
- A Comprehensive System-on-Chip Logic DiagnosisYoussef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer. 237-242 [doi]
- On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon ValidationXiao Liu, Qiang Xu. 243-248 [doi]
- HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoCMohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta. 249-254 [doi]
- Enhance Profiling-Based Scan Chain Diagnosis by Pattern MaskingWu-Tung Cheng, Yu Huang. 255-260 [doi]
- Maximal Resilience for Reliability and Yield Enhancement in Interconnect StructureChih-Yun Pai, Katherine Shu-Min Li. 261-266 [doi]
- At-speed Test of High-Speed DUT Using Built-Off Test InterfaceJoonsung Park, Jae-Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh. 269-274 [doi]
- Rapid Radio Frequency Amplitude and Phase Distortion Measurement Using Amplitude Modulated StimulusShreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee. 277-282 [doi]
- Digitally Assisted Concurrent Built-In Tuning of RF Systems Using Hamming Distance Proportional SignaturesShyam Kumar Devarakond, Shreyas Sen, Vishwanath Natarajan, Aritra Banerjee, Hyun Choi, Ganesh Srinivasan, Abhijit Chatterjee. 283-288 [doi]
- The Test Ability of an Adaptive Pulse Wave for ADC TestingXiaoqin Sheng, Hans G. Kerkhoff. 289-294 [doi]
- Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density EstimationKe Huang, Haralampos-G. D. Stratigopoulos, Salvador Mir. 295-298 [doi]
- Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer TestWei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty. 301-306 [doi]
- Circuit Topology-Based Test Pattern Generation for Small-Delay DefectsSandeep Kumar Goel, Krishnendu Chakrabarty, Mahmut Yilmaz, Ke Peng, Mohammad Tehranipoor. 307-312 [doi]
- Seed Ordering and Selection for High Quality Delay TestTomokazu Yoneda, Michiko Inoue, Akira Taketani, Hideo Fujiwara. 313-318 [doi]
- An Efficient Algorithm for Finding a Universal Set of Testable Long PathsZijian He, Tao Lv, Huawei Li, Xiaowei Li. 319-324 [doi]
- Distinguishing Resistive Small Delay Defects from Random Parameter VariationsXi Qian, Adit D. Singh. 325-330 [doi]
- A Noise-Aware Hybrid Method for SDD Pattern Grading and SelectionKe Peng, Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Tehranipoor. 331-336 [doi]
- Thermal Safe High Level Test Synthesis for Hierarchical TestabilityTung-Hua Yeh, Sying-Jyan Wang. 337-342 [doi]
- A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement CircuitKentaroh Katoh, Kazuteru Namba, Hideo Ito. 343-348 [doi]
- On Bias in Transition Coverage of Test Sets for Path Delay FaultsIrith Pomeranz, Sudhakar M. Reddy. 349-352 [doi]
- Adaptive Low Shift Power Test Pattern Generator for Logic BISTXijiang Lin, Janusz Rajski. 355-360 [doi]
- Power Supply Noise Reduction in Broadcast-Based Compression Environment for At-speed Scan TestingChun-Yong Liang, Meng-Fan Wu, Jiun-Lang Huang. 361-366 [doi]
- Modified Scan Flip-Flop for Low Power TestingAmit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh. 367-370 [doi]
- Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test PowerZhiqiang You, Jiedi Huang, Michiko Inoue, Jishun Kuang, Hideo Fujiwara. 371-374 [doi]
- A Test Integration Methodology for 3D Integrated CircuitsChe-Wei Chou, Jin-Fu Li, Ji-Jan Chen, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 377-382 [doi]
- Performance Characterization of TSV in 3D IC via Sensitivity AnalysisJhih-Wei You, Shi-Yu Huang, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu. 389-394 [doi]
- Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process VariationNima Aghaee, Zhiyuan He, Zebo Peng, Petru Eles. 395-398 [doi]
- Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory TestingS. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay. 401-406 [doi]
- New Microcode s Generation Technique for Programmable Memory Built-In Self TestNurQamarina MohdNoor, Azilah Saparon, Yusrina Yusof, Mahmud Adnan. 407-412 [doi]
- Software-Based Self-Testing of Processors Using Expanded InstructionsYing Zhang, Huawei Li, Xiaowei Li. 415-420 [doi]
- Mimicking of Functional State Space with Structural Tests for the Diagnosis of Board-Level Functional FailuresHongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty. 421-428 [doi]
- Optimization and Selection of Diagnosis-Oriented Fault-Insertion Points for System TestZhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty. 429-432 [doi]
- Test Cost Analysis for 3D Die-to-Wafer StackingMottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen. 435-441 [doi]
- Mining Complex Boolean Expressions for Sequential Equivalence CheckingNeha Goel, Michael S. Hsiao, Naren Ramakrishnan, Mohammed J. Zaki. 442-447 [doi]
- On-the-Fly Reduction of Stimuli for Functional VerificationQi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Weiwu Hu. 448-454 [doi]
- Test Time Analysis for IEEE P1687Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson, Erik Larsson. 455-460 [doi]