| 3 | -- | 4 | Daniel J. Fleming. Preface |
| 5 | -- | 22 | Robert F. Sechler, Gregory F. Grohoski. Design at the system level with VLSI CMOS |
| 23 | -- | 32 | Robert F. Sechler. Interconnect design with VLSI CMOS |
| 33 | -- | 42 | Kerry Bernstein, John E. Bertsch, Lawrence G. Heller, Edward J. Nowak, Francis R. White. Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor |
| 43 | -- | 50 | Toshio Sunaga, Koji Hosokawa, Sang H. Dhong, Koji Kitamura. A 64Kb - 32 DRAM for graphics applications |
| 51 | -- | 62 | Wayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter. Multipurpose DRAM architecture for optimal power, performance, and product flexibility |
| 63 | -- | 72 | Daniel M. Kuchta, Herschel A. Ainspan, Frank J. Canora, Richard P. Schneider Jr.. Performance of fiber-optic data links using 670-nm cw VCSELs and a monolithic Si photodetector and CMOS preamplifier |
| 73 | -- | 82 | John F. Ewen, Mehmet Soyuer, Albert X. Widmer, Kevin R. Wrenner, Benjamin D. Parker, Herschel A. Ainspan. CMOS circuits for Gb/s serial data communication |
| 83 | -- | 92 | Hyun J. Shin, Dale J. Pearson, Scott K. Reynolds, Andrew C. Megdanis, Sudhir M. Gowda, Kevin R. Wrenner. Custom design of CMOS low-power high-performance digital signal-processing macro for hard-disk-drive applications |
| 93 | -- | 104 | Roland A. Bechade, Robert M. Houle. Digital delay line clock shapers and multipliers |
| 105 | -- | 112 | Sang H. Dhong, Masahiro Tanaka, Steven W. Tomashot, Toshiaki Kirihata. A low-noise TTL-compatible CMOS off-chip driver circuit |
| 113 | -- | 130 | Pradip Bose, S. Surya. Architectural timing verification of CMOS RISC processors |
| 131 | -- | 148 | Reinaldo A. Bergamaschi, Richard A. O Connor, Leon Stok, Michael Z. Moricz, Shiv Prakash, Andreas Kuehlmann, D. Sreenivasa Rao. High-level synthesis in an industrial environment |
| 149 | -- | 166 | Andreas Kuehlmann, Arvind Srinivasan, David P. LaPotin. Verity - A formal verification program for custom CMOS circuits |
| 167 | -- | 188 | Eric Adler, John K. DeBrosse, Stephen F. Geissler, Steven J. Holmes, Mark D. Jaffe, Jeffrey B. Johnson, Charles W. Koburger III, Jerome B. Lasky, Brian Lloyd, Glen L. Miles, James S. Nakos, Wendell P. Noble Jr., Steven H. Voldman, Michael Armacost, Richard Ferguson. The evolution of IBM CMOS DRAM technology |
| 189 | -- | 200 | Donald G. Chesebro, James W. Adkisson, Lyman R. Clark, Steven N. Eslinger, Margaret A. Faucher, Steven J. Holmes, Raymond P. Mallette, Edward J. Nowak, Edward W. Sengle, Steven H. Voldman, Thomas W. Weeks. Overview of gate linewidth control in the manufacture of CMOS logic chips |
| 201 | -- | 214 | George A. Leonovich, Anthony P. Franchino, William J. Miller, Uh-Po Eric Tsou. Integrated cost and productivity learning in CMOS semiconductor manufacturing |
| 215 | -- | 228 | Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman. A half-micron CMOS logic generation |
| 229 | -- | 244 | G. G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, J. Y.-C. Sun, Michael R. Polcari, Bijan Davari. CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications |
| 245 | -- | 260 | Yuan Taur, Yuh-Jier Mii, David J. Frank, H.-S. Philip Wong, Douglas A. Buchanan, Shalom J. Wind, Stephen A. Rishton, Watson A. Sai-Halasz, Edward J. Nowak. CMOS scaling into the 21st century: 0.1 µm and beyond |