André Seznec - researchr alias

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2011

2010

Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cache missesPierre Michaud, Yiannakis Sazeides, André Seznec. cf 2010: 237-246 [doi]

A Phase Change Memory as a Secure Main MemoryAndré Seznec. cal, 9(1):5-8, 2010. [doi]

37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, FranceAndré Seznec, Uri Weiser, Ronny Ronen, editors, ACM, 2010.

2009

Zero-content augmented cachesJulien Dusser, Thomas Piquet, André Seznec. ics 2009: 46-55 [doi]

High Performance Embedded Architectures and Compilers, Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. ProceedingsAndré Seznec, Joel S. Emer, Michael F. P. O Boyle, Margaret Martonosi, Theo Ungerer, editors, Volume 5409 of Lecture Notes in Computer Science, Springer, 2009. [doi]

Parallel HAVEGEAlin Suciu, Tudor Carean, André Seznec, Kinga Marton. ppam 2010: 145-154 [doi]

Fetch Gating Control through Speculative Instruction Window WeightingHans Vandierendonck, André Seznec. thipeac, 2:128-148, 2009. [doi]

2008

Speculative return address stack management revisitedHans Vandierendonck, André Seznec. taco, 5(3), 2008. [doi]

2007

2006

A case for a complexity-effective, width-partitioned microarchitectureOlivier Rochecouste, Gilles Pokam, André Seznec. taco, 3(3):295-326, 2006. [doi]

2005

2004

The SAC Test: A New Randomness Test, with Some Applications to PRNG AnalysisJulio César Hernández Castro, José María Sierra, André Seznec. iccsa 2004: 960-967 [doi]

IATO: A Flexible EPIC Simulation EnvironmentAmaury Darsch, André Seznec. sbac-pad 2004: 58-65 [doi]

CASH: Revisiting Hardware Sharing in Single-Chip Parallel ProcessorsRomain Dolbeau, André Seznec. jilp, 6, 2004.

Topic 8: Parallel Computer Architecture and Instruction-Level ParallelismKemal Ebcioglu, Wolfgang Karl, André Seznec, Marco Aldinucci. europar 2004: 506 [doi]

Proceedings of the 18th Annual International Conference on Supercomputing, ICS 2004, Saint Malo, France, June 26 - July 01, 2004Paul Feautrier, James Goodman, André Seznec, editors, ACM, 2004.

Speculative software management of datapath-width for energy optimizationGilles Pokam, Olivier Rochecouste, André Seznec, François Bodin. lctrts 2004: 78-87 [doi]

Concurrent Support of Multiple Page Sizes on a Skewed Associative TLBAndré Seznec. TC, 53(7):924-927, 2004. [doi]

2003

Effective ahead Pipelining of Instruction Block Address GenerationAndré Seznec, Antony Fraboulet. isca 2003: 241-252 [doi]

HAVEGE: A user-level software heuristic for generating empirically strong random numbersAndré Seznec, Nicolas Sendrier. tomacs, 13(4):334-346, 2003. [doi]

2002

2001

2000

Combining Light Static Code Annotation and Instruction-Set Emulation for Flexible and Efficient On-the-Fly Simulation (Research Note)Thierry Lafage, André Seznec. europar 2000: 178-182 [doi]

Handling Global Constraints in Compiler StrategyErven Rohou, François Bodin, Christine Eisenbeis, André Seznec. ijpp, 28(4):325-345, 2000.

1999

Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous MultithreadingSébastien Hily, André Seznec. hpca 1999: 64 [doi]

Code Cloning Tracing: A Pay per Trace ApproachThierry Lafage, André Seznec, Erven Rohou, François Bodin. europar 1999: 1265-1268 [doi]

Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar ProcessorsPierre Michaud, André Seznec, Stéphan Jourdan. IEEEpact 1999: 2-10 [doi]

1998

1997

1996

Don t Use the Page Number, But a Pointer To ItAndré Seznec. isca 1996: 104-113 [doi]

Multiple-Block Ahead Branch PredictorsAndré Seznec, Stéphan Jourdan, Pascal Sainrat, Pierre Michaud. asplos 1996: 116-127

1995

Skewed Associativity Enhances Performance PredictabilityFrançois Bodin, André Seznec. isca 1995: 265-274 [doi]

About Cache Associativity in Low-Cost Shared Memory Multi-MicroprocessorsNathalie Drach, Alain Gefflaut, Philippe Joubert, André Seznec. ppl, 5:475-487, 1995.

DASC CacheAndré Seznec. hpca 1995: 134-143

Odd Memory Systems: A New ApproachAndré Seznec, Jacques Lenfant. jpdc, 26(2):248-256, 1995.

1994

Interleaved Parallel SchemesAndré Seznec, Jacques Lenfant. tpds, 5(12):1329-1334, 1994. [doi]

Decoupled Sectored Caches: Conciliating Low Tag Implementation Cost and Low Miss RatioAndré Seznec. isca 1994: 384-393

1993

1992

Controlling and sequencing a heavily pipelined floating-point operatorAndré Seznec, Karl Courtel. euromicro 1992: 111-114 [doi]

Interleaved Parallel Schemes: Improving Memory Throughput on SupercomputersAndré Seznec, Jacques Lenfant. isca 1992: 246-255

1989

A asynchronous buffering network for tightly coupled multiprocessorsYvon Jégou, André Seznec. ics 1989: 331-340 [doi]

1988

Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cacheAndré Seznec, Yvon Jégou. ics 1988: 611-620 [doi]

Synchronizing Processors Through Memory Requests in a Tightly Coupled MultiprocessorAndré Seznec, Yvon Jégou. isca 1988: 393-400

1987

A New Interconnection Network for SIMD Computers: The Sigma NetworkAndré Seznec. TC, 36(7):794-801, 1987.

Optimizing Memory Throughput In a Tightly Coupled MultiprocessorAndré Seznec, Yvon Jégou. icpp 1987: 344-346

1986

Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor EnvironmentsYvon Jégou, André Seznec. jpdc, 3(4):508-526, 1986.

Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor EnvironmentsYvon Jégou, André Seznec. icpp 1986: 487-494

An Efficient Routing Control Unit for the SIGMA Network E(4)André Seznec. isca 1986: 158-168