Sangyeun Cho - researchr alias

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Viewing Publication 1 - 94 from 94

2024

Self-Encrypting Drive Evolving Toward Multitenant Cloud ComputingJisoo Kim, Mungyu Bae, YeonSung Chu, Moon Chan Park, Dongwon Park, Dawoon Jung, Sangyeun Cho. Computer, 57(2):79-90, February 2024. [doi]

2023

TiDedup: A New Distributed Deduplication Architecture for CephMyoungwon Oh, Sungmin Lee, Samuel Just, Youngjin Yu, Duck-Ho Bae, Sage A. Weil, Sangyeun Cho, Heon Y. Yeom. usenix 2023: 117-131 [doi]

2018

2B-SSD: The Case for Dual, Byte- and Block-Addressable Solid-State DrivesDuck-Ho Bae, Insoon Jo, Youra Choi, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong. isca 2018: 425-438 [doi]

FStream: Managing Flash Streams in the File SystemEunhee Rho, Kanchan Joshi, Seung-Uk Shin, Nitesh Jagadeesh Shetty, Joo Young Hwang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong. FAST 2018: 257-264 [doi]

Barrier-Enabled IO Stack for Flash StorageYoujip Won, Jaemin Jung, Gyeongyeol Choi, Joontaek Oh, Seongbae Son, Joo Young Hwang, Sangyeun Cho. FAST 2018: 211-226 [doi]

Bringing Order to Chaos: Barrier-Enabled I/O Stack for Flash StorageYoujip Won, Joontaek Oh, Jaemin Jung, Gyeongyeol Choi, Seongbae Son, Joo Young Hwang, Sangyeun Cho. tos, 14(3), 2018. [doi]

2017

Jointly optimizing task granularity and concurrency for in-memory mapreduce frameworksJonghyun Bae, Hakbeom Jang, Wenjing Jin, Jun Heo, Jaeyoung Jang, Joo Young Hwang, Sangyeun Cho, Jae W. Lee. bigdataconf 2017: 130-140 [doi]

An analytical model based on performance demand of workload for energy-efficient heterogeneous multicore systemsMin-Kwan Kee, Hong-Yeol Lim, Gi-Ho Park, Sangyeun Cho. jpdc, 100:172-180, 2017. [doi]

2016

Biscuit: A Framework for Near-Data Processing of Big Data WorkloadsBoncheol Gu, Andre S. Yoon, Duck-Ho Bae, Insoon Jo, Jinyoung Lee, Jonghyun Yoon, Jeong-Uk Kang, MoonSang Kwon, Chanho Yoon, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang. isca 2016: 153-165 [doi]

YourSQL: A High-Performance Database System Leveraging In-Storage ComputingInsoon Jo, Duck-Ho Bae, Andre S. Yoon, Jeong-Uk Kang, Sangyeun Cho, Daniel D. G. Lee, Jaeheon Jeong. pvldb, 9(12):924-935, 2016. [doi]

In-storage processing of database scans and joinsSungchan Kim, Hyunok Oh, Chanik Park, Sangyeun Cho, Sang-Won Lee, Bongki Moon. isci, 327:183-200, 2016. [doi]

Symbol Shifting: Tolerating More Faults in PCM BlocksRakan Maddah, Sangyeun Cho, Rami G. Melhem. TC, 65(7):2270-2283, 2016. [doi]

Design and implementation of a mobile storage leveraging the DRAM interfaceSungyong Seo, Youngjin Cho, Youngkwang Yoo, Otae Bae, Jaegeun Park, Heehyun Nam, Sunmi Lee, Yongmyung Lee, Seungdo Chae, MoonSang Kwon, Jin Hyeok Choi, Sangyeun Cho, Jaeheon Jeong, Duckhyun Chang. hpca 2016: 531-542 [doi]

2015

2014

2013

2012

2011

MAESTRO: Orchestrating predictive resource management in future multicore systemsSangyeun Cho, Socrates Demetriades. ahs 2011: 1-8 [doi]

BarrierWatch: characterizing multithreaded workloads across and within program-defined epochsSocrates Demetriades, Sangyeun Cho. cf 2011: 5 [doi]

C-AMTE: A location mechanism for flexible cache management in chip multiprocessorsMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. jpdc, 71(6):889-896, 2011. [doi]

Cache equalizer: a placement mechanism for chip multiprocessor distributed shared cachesMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. hipeac 2011: 177-186 [doi]

Advanced hashing schemes for packet forwarding using set associative memory architecturesMichel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem. jpdc, 71(1):1-15, 2011. [doi]

A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined TriesMichel Hanna, Sangyeun Cho, Rami G. Melhem. networking 2011: 406-419 [doi]

Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data ReuseLei Jin, Sangyeun Cho. TC, 60(4):526-537, 2011. [doi]

Dynamic co-management of persistent RAM main memory and storage resourcesJu-Young Jung, Sangyeun Cho. cf 2011: 13 [doi]

PRISM: Zooming in persistent RAM storage behaviorJu-Young Jung, Sangyeun Cho. ispass 2011: 22-31 [doi]

Fast, Energy Efficient Scan inside Flash MemorySungchan Kim, Hyunok Oh, Chanik Park, Sangyeun Cho, Sang-Won Lee. VLDB 2011: 36-43 [doi]

In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order TracesKiyeon Lee, Sangyeun Cho. mascots 2011: 126-135 [doi]

DEFCAM: A design and evaluation framework for defect-tolerant cache memoriesHyunjin Lee, Sangyeun Cho, Bruce R. Childers. taco, 8(3):17, 2011. [doi]

CloudCache: Expanding and shrinking private cachesHyunjin Lee, Sangyeun Cho, Bruce R. Childers. hpca 2011: 219-230 [doi]

Scalable Multi-cache Simulation Using GPUsMichael Moeng, Sangyeun Cho, Rami G. Melhem. mascots 2011: 159-167 [doi]

An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth SharingTaecheol Oh, Kiyeon Lee, Sangyeun Cho. mascots 2011: 150-158 [doi]

COMeT: Continuous Online Memory TestMusfiq Rahman, Bruce R. Childers, Sangyeun Cho. prdc 2011: 109-118 [doi]

2010

On the Interplay of Parallelization, Program Performance, and Energy ConsumptionSangyeun Cho, Rami G. Melhem. tpds, 21(3):342-353, 2010. [doi]

A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip MultiprocessorsMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. cal, 9(1):29-32, 2010. [doi]

An intra-tile cache set balancing schemeMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. IEEEpact 2010: 549-550 [doi]

PERFECTORY: A Fault-Tolerant Directory Memory ArchitectureHyunjin Lee, Sangyeun Cho, Bruce R. Childers. TC, 59(5):638-650, 2010. [doi]

Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approachHyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho. SPE, 40(3):239-258, 2010. [doi]

StimulusCache: Boosting performance of chip multiprocessors with excess cacheHyunjin Lee, Sangyeun Cho, Bruce R. Childers. hpca 2010: 1-12 [doi]

StealthWorks: Emulating Memory ErrorsMusfiq Rahman, Bruce R. Childers, Sangyeun Cho. RV 2010: 360-367 [doi]

A content-aware block placement algorithm for reducing PRAM storage bit writesBrian Wongchaowart, Marian Kamal Iskander, Sangyeun Cho. mss 2010: 1-11 [doi]

2009

Augmented FIFO Cache Replacement Policies for Low-Power Embedded ProcessorsSangyeun Cho, Lory Al Moakar. jcsc, 18(6):1081-1092, 2009. [doi]

Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and enduranceSangyeun Cho, Hyunjin Lee. micro 2009: 347-357 [doi]

Dynamic cache clustering for chip multiprocessorsMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. ics 2009: 56-67 [doi]

ACM: An Efficient Approach for Managing Shared Caches in Chip MultiprocessorsMohammad Hammoud, Sangyeun Cho, Rami G. Melhem. hipeac 2009: 355-372 [doi]

CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP LookupMichel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem. networking 2009: 756-769 [doi]

Progressive hashing for packet processing using set associative memoryMichel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem. ancs 2009: 153-162 [doi]

SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip MultiprocessorsLei Jin, Sangyeun Cho. IEEEpact 2009: 361-371 [doi]

Accurately approximating superscalar processor performance from tracesKiyeon Lee, Shayne Evans, Sangyeun Cho. ispass 2009: 238-248 [doi]

An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip MultiprocessorTaecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho. isvlsi 2009: 181-186 [doi]

2008

Early prediction of product performance and yield via technology benchmarkChoongyeun Cho, Daeik D. Kim, Jonghae Kim, Daihyun Lim, Sangyeun Cho. cicc 2008: 205-208 [doi]

TPTS: A Novel Framework for Very Fast Manycore Processor Architecture SimulationSangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng. icpp 2008: 446-453 [doi]

Guest Editors Introduction: Interaction of Many-Core Computer Architecture and Operating SystemsSangyeun Cho, Tao Li, Onur Mutlu. micro, 28(3):2-5, 2008. [doi]

An Efficient Hardware-Based Multi-hash Scheme for High Speed IP LookupSocrates Demetriades, Michel Hanna, Sangyeun Cho, Rami G. Melhem. hoti 2008: 103-110 [doi]

Taming Single-Thread Program Performance on Many Distributed On-Chip L2 CachesLei Jin, Sangyeun Cho. icpp 2008: 487-494 [doi]

Preliminary studies to develop a ubiquitous computing and health-monitoring system for wheelchair usersJongbae Kim, Sangyeun Cho, Seung-Jae Kim. bodynets 2011: 3 [doi]

2007

I-cache multi-banking and vertical interleavingSangyeun Cho. glvlsi 2007: 14-19 [doi]

Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time SystemsSangyeun Cho, Lei Jin, Kiyeon Lee. rtcsa 2007: 3-11 [doi]

A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI TechnologyChoongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski. isqed 2007: 699-702 [doi]

Corollaries to Amdahl s Law for EnergySangyeun Cho, Rami G. Melhem. cal, 7(1):25-28, 2007. [doi]

CA-RAM: A High-Performance Memory Substrate for Search-Intensive ApplicationsSangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem. ispass 2007: 230-241 [doi]

Performance of Graceful Degradation for Cache FaultsHyunjin Lee, Sangyeun Cho, Bruce R. Childers. isvlsi 2007: 409-415 [doi]

Exploring the interplay of yield, area, and performance in processor cachesHyunjin Lee, Sangyeun Cho, Bruce R. Childers. iccd 2007: 216-223 [doi]

2006

Managing Distributed, Shared L2 Caches through OS-Level Page AllocationSangyeun Cho, Lei Jin. micro 2006: 455-468 [doi]

Reducing cache traffic and energy with macro data loadLei Jin, Sangyeun Cho. islped 2006: 147-150 [doi]

A flexible data to L2 cache mapping approach for future multicore processorsLei Jin, Hyunjin Lee, Sangyeun Cho. ACMmsp 2006: 92-101 [doi]

2001

A Low-Power Cache Design for CalmRISC:::TM:::-Based SystemsSangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong. iccd 2001: 394-399

A High-Bandwidth Memory Pipeline for Wide Issue ProcessorsSangyeun Cho, Pen-Chung Yew, Gyungho Lee. TC, 50(7):709-723, 2001. [doi]

1999

Coherence and Replacement Protocol of DICE-A Bus-Based COMA MultiprocessorSangyeun Cho, Jinseok Kong, Gyungho Lee. jpdc, 57(1):14-32, 1999.

Access Region Locality for High-Bandwidth Processor Memory System DesignSangyeun Cho, Pen-Chung Yew, Gyungho Lee. euromicro 1999: 136-146 [doi]

Design of a bus-based shared-memory multiprocessor DICEGyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney. mam, 22(7):403-411, 1999. [doi]

1998

On timing constraints of snooping in a bus-based COMA multiprocessorSangyeun Cho, Jinseok Kong, Gyungho Lee. mam, 21(5):313-318, 1998. [doi]

High-Level Information - An Approach for Integrating Front-End and Back-End CompilersSangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Stephen J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David J. Lilja, Pen-Chung Yew. icpp 1998: 346-355 [doi]

1996

Reducing Coherence Overhead in Shared-Bus MultiprocessorsSangyeun Cho, Gyungho Lee. europar 1996: 492-497

Global Bus Design of a Bus-Based COMA Multiprocessor DICEGyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney. iccd 1996: 231 [doi]

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