Abstract is missing.
- High-speed architectures for parallel long BCH encodersXinmiao Zhang, Keshab K. Parhi. 1-6 [doi]
- Optimal partitioning of globally asychronous locally synchronous processor arraysAdhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili. 7-12 [doi]
- High level techniques for power-grid noise immunityAzadeh Davoodi, Vishal Khandelwal, Ankur Srivastava. 13-18 [doi]
- TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnectsSoroush Abbaspour, Amir H. Ajami, Massoud Pedram, Emre Tuncer. 19-24 [doi]
- Modeling of transmission lines with EM wave coupling by the finite difference quadrature methodQinwei Xu, Pinaki Mazumder. 25-28 [doi]
- Simplified delay design guidelines for on-chip global interconnectsLiang Zhang, Wentai Liu, Rizwan Bashirullah, John Wilson, Paul D. Franzon. 29-32 [doi]
- Design and optimization of MOS current mode logic for parameter variationsHassan Hassan, Mohab Anis, Mohamed I. Elmasry. 33-38 [doi]
- A 2 Gb/s balanced AES crypto-chip implementationFrank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin. 39-44 [doi]
- Quality-of-service and error control techniques for network-on-chip architecturesPraveen Vellanki, Nilanjan Banerjee, Karam S. Chatha. 45-50 [doi]
- Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithmZhiyuan Yan, Dilip V. Sarwate. 51-56 [doi]
- A compact DSP core with static floating-point unit & its microcode generationTay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen. 57-60 [doi]
- An efficient architecture for lifting-based two-dimensional discrete wavelet transformsSankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell. 61-66 [doi]
- A graph based simplex method for the integer minimum perturbation problem with sum and difference constraintsAlexey Lvov, Fook-Luen Heng. 67-72 [doi]
- ARCS: an architectural level communication driven simulatorDave Nellans, Vamshi Krishna Kadaru, Erik Brunvand. 73-77 [doi]
- A fast and efficient heuristic ESOP minimization algorithmStergios Stergiou, K. Daskalakis, George K. Papakonstantinou. 78-81 [doi]
- A memory aware behavioral synthesis tool for real-time VLSI circuitsGwenolé Corre, Eric Senn, Nathalie Julien, Eric Martin. 82-85 [doi]
- Low-power weighted pseudo-random BIST using special scan cellsShalini Ghosh, Eric MacDonald, Sugato Basu, Nur A. Touba. 86-91 [doi]
- Efficient formal verification of pipelined processors with instruction queuesMiroslav N. Velev. 92-95 [doi]
- Evaluation of heuristic techniques for test vector orderingHamidreza Hashempour, Fabrizio Lombardi. 96-99 [doi]
- Logic-level analysis of high-level faultsFranco Fummi, Graziano Pravadelli. 100-103 [doi]
- A stacked antenna broad-band RFID front-end for UHF and microwave bandsVijay Pillai, Harley Heinrich, K. V. S. Rao, Rene Martinez. 104-108 [doi]
- NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architecturesDebayan Bhaduri, Sandeep K. Shukla. 109-112 [doi]
- Constructive benchmarking for placementDavid A. Papa, Saurabh N. Adya, Igor L. Markov. 113-118 [doi]
- Design of superbuffers in sub-100nm CMOS technologies with significant gate leakageAli Bastani, Charles A. Zukowski. 119-122 [doi]
- Improving FSM evolution with progressive fitness functionsJason W. Horihan, Yung-Hsiang Lu. 123-126 [doi]
- Fault simulation and random test generation for speed-independent circuitsFeng Shi, Yiorgos Makris. 127-130 [doi]
- Minimal period retiming under process variationsJia Wang, Hai Zhou. 131-135 [doi]
- Simulation of reconfigurable memory core yieldMarco Ottavi, Xiaopeng Wang, Fred J. Meyer, Fabrizio Lombardi. 136-140 [doi]
- The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGAJong-Ru Guo, Chao You, Paul F. Curran, Michael Chu, Kuan Zhou, Jiedong Diao, A. George, Russell P. Kraft, John F. McDonald. 141-144 [doi]
- On-chip delay measurement for silicon debugRamyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham. 145-148 [doi]
- Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching techniqueYarallah Koolivand, Ali Zahabi, Nasser Masoumi. 149-153 [doi]
- A simple DDS architecture with highly efficient sine function lookup tableZhengyu Wang, M.-C. Frank Chang, Jessica Chiatai Chou. 154-157 [doi]
- Leakage current reduction by new technique in standby modeA. Amirabadi, Javid Jaffari, Ali Afzali-Kusha, Mehrdad Nourani, Ali Khaki-Firooz. 158-161 [doi]
- Macro-models for high level area and power estimation on FPGAsTianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee. 162-165 [doi]
- Leakage power minimization for the synthesis of parallel multiplier circuitsKeoncheol Shin, Taewhan Kim. 166-169 [doi]
- Tuning data replication for improving behavior of MPSoC applicationsOzcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin, Ibrahim Kolcu. 170-173 [doi]
- Self-resetting stage logic pipelinesAbdel Ejnioui, Abdelhalim Alsharqawi. 174-177 [doi]
- A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductorsShaolei Quan, Chin-Long Wey. 178-182 [doi]
- A CMOS elliptic low-pass switched capacitor ladder filter for video communication using bilinear implementationMohammad Moghaddam Tabrizi, Amir Amirabadi. 183-186 [doi]
- FIFO power optimization for on-chip networksSudarshan Banerjee, Nikil D. Dutt. 187-191 [doi]
- Structured interconnect architecture: a solution for the non-scalability of bus-based SoCsCristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh. 192-195 [doi]
- A device-level placement with multi-directional convex clusteringTakashi Nojima, Yasuhiro Takashima, Shigetoshi Nakatake, Yoji Kajitani. 196-201 [doi]
- A new paradigm for general architecture routingMartin Paluszewski, Pawel Winter, Martin Zachariasen. 202-207 [doi]
- An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performanceHasan Arslan, Shantanu Dutt. 208-213 [doi]
- On legalization of row-based placementsAndrew B. Kahng, Igor L. Markov, Sherief Reda. 214-219 [doi]
- Equidistance routing in high-speed VLSI layout designYukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi. 220-223 [doi]
- Mitigating static power in current-sensed interconnectsVishak Venkatraman, Atul Maheshwari, Wayne Burleson. 224-229 [doi]
- Characterization of logic circuit techniques for high leakage CMOS technologiesPhillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky. 230-235 [doi]
- Energy-efficient bus encoding for LCD displaysAlberto Bocca, Sabino Salerno, Enrico Macii, Massimo Poncino. 240-243 [doi]
- Power macromodeling of global interconnects considering practical repeater insertionYuantao Peng, Xun Liu. 244-247 [doi]
- Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow modelsHiren D. Patel, Sandeep K. Shukla. 248-253 [doi]
- Estimating detection probability of interconnect opens using stuck-at testsShalini Ghosh, F. Joel Ferguson. 254-259 [doi]
- VLSI implementation of an automatic Q tuning systemRoghoyeh Salmeh, Brent Maundy. 260-265 [doi]
- A practical approach to modeling skin effect in on-chip interconnectsBhaskar Mukherjee, Lei Wang, Andrea Pacelli. 266-270 [doi]
- A high level language for pre-layout extraction in parasite-aware analog circuit synthesisRaoul F. Badaoui, Hemanth Sampath, Anuradha Agarwal, Ranga Vemuri. 271-276 [doi]
- Power-efficient ASIC synthesis of cryptographic sboxesGuido Bertoni, Marco Macchetti, Luca Negri, Pasqualina Fragneto. 277-281 [doi]
- Practical slicing and non-slicing block-packing without simulated annealingHayward H. Chan, Igor L. Markov. 282-287 [doi]
- Assertion-based automated functional vectors generation using constraint logic programmingTun Li, Yang Guo, Sikun Li. 288-291 [doi]
- Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packagesChung-Seok (Andy) Seo, Abhijit Chatterjee, Sang-Yeon Cho, Nan M. Jokerst. 292-297 [doi]
- Design of a nanosensor array architectureWei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. 298-303 [doi]
- A binary--search switched--current sensing scheme for 4-state MRAMEdward K. S. Au, Wing-Hung Ki, Wai Ho Mow, Silas T. Hung, Catherine Y. Wong. 304-307 [doi]
- Design of a 5-Gb/s PRBS generator in 0.18µm CMOS processAdam O. Lee, Robert J. Weber. 308-311 [doi]
- Analysis and verification of interconnected rings as clock distribution networksManuel Salim Maza, Mónico Linares Aranda. 312-315 [doi]
- LFSR-based BIST for analog circuits using slope detectionHongjoong Shin, Hak-soo Yu, Jacob A. Abraham. 316-321 [doi]
- Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancementChin-Long Wey, Mohammad Athar Khalil, Jim Liu, Gregory Wierzba. 322-327 [doi]
- An efficient linearity test for on-chip high speed ADC and DAC using loop-backJi Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham. 328-331 [doi]
- Automatic cell placement for quantum-dot cellular automataRamprasad Ravichandran, Nihal Ladiwala, Jean Nguyen, Michael T. Niemier, Sung Kyu Lim. 332-337 [doi]
- Timing, energy, and thermal performance of three-dimensional integrated circuitsShamik Das, Anantha Chandrakasan, Rafael Reif. 338-343 [doi]
- SET-based nano-circuit simulation and design method using HSPICEFengming Zhang, Rui Tang, Yong-Bin Kim. 344-347 [doi]
- SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuitsKatsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi. 348-353 [doi]
- CESC: a visual formalism for specification and verification of SoCsAmbar A. Gadkari, S. Ramesh, Rubin A. Parekhji. 354-357 [doi]
- Cluster miss prediction for instruction caches in embedded networking applicationsKenneth E. Batcher, Robert A. Walker. 358-363 [doi]
- The design of the fixed point unit for the z990 microprocessorFadi Busaba, Timothy J. Slegel, Steven R. Carlough, Christopher A. Krygowski, John G. Rell. 364-367 [doi]
- How to reduce aliasing in linear analog testingZhen Guo. 368-371 [doi]
- A keyword match processor architecture using content addressable memoryLong Bu, John A. Chandy. 372-376 [doi]
- A high performance CMOS direct down conversion mixer for UWB systemAnh-Tuan Phan, Chang-Wan Kim, Min-Suk Kang, Sang-Gug Lee, Chun-Deok Su, Hoon-Tae Kim. 377-380 [doi]
- Multi-peak bandwidth enhancement technique for multistage amplifiersM. Reza Samadi, Aydin I. Karsilayan. 381-384 [doi]
- Orthogonal hypergraph routing for improved visibilityThomas Eschbach, Wolfgang Günther, Bernd Becker. 385-388 [doi]
- Low power ATPG for path delay faultsMahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas. 389-392 [doi]
- Low energy FPGA interconnect designRohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek. 393-396 [doi]
- Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAsDavid Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee. 397-400 [doi]
- RESTA: a robust and extendable symbolic timing analysis toolKundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein. 407-412 [doi]
- Cycle-accurate power analysis for multiprocessor systems-on-a-chipMirko Loghi, Massimo Poncino, Luca Benini. 410-406 [doi]
- Performance enhancement in phased logic circuits using automatic slack-matching buffer insertionKenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver. 413-416 [doi]
- A new test pattern generator for high defect coverage in a BIST environmentC. Laoudias, Dimitris Nikolos. 417-420 [doi]
- An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512)Luigi Dadda, Marco Macchetti, Jeff Owen. 421-425 [doi]
- Design and characterization of an and-or-inverter (AOI) gate for QCA implementationJing Huang, Mariam Momenzadeh, Mehdi Baradaran Tahoori, Fabrizio Lombardi. 426-429 [doi]
- Energy estimation of peripheral devices in embedded systemsOzgur Celebican, Tajana Simunic Rosing, Vincent John Mooney III. 430-435 [doi]
- A comparison between mask- and field-programmable routing structures on industrial FPGA architecturesLuca Macchiarulo, Consolato F. Caccamo, Davide Pandini. 436-439 [doi]
- Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processorsMatteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon. 440-443 [doi]
- Modified booth truncated multipliersAlok A. Katkar, James E. Stine. 444-447 [doi]
- Design methodology for semi custom processor coresVictor V. Zyuban, Sameh W. Asaad, Thomas W. Fox, Anne-Marie Haen, Daniel Littrell, Jaime H. Moreno. 448-452 [doi]
- An FPGA implementation of an elliptic curve processor GF(2:::m:::)Nele Mentens, Siddika Berna Örs, Bart Preneel. 454-457 [doi]
- Hardware architecture and FPGA implementation of a type-2 fuzzy systemMiguel A. Melgarejo, Carlos Andrés Peña-Reyes. 458-461 [doi]
- High-speed systolic architectures for finite field inversion and divisionZhiyuan Yan, Dilip V. Sarwate. 462-465 [doi]