Table of Contents

• Minimal area test points for deterministic patternsYingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer. 1-7 [doi]
• BIST-RM: BIST-assisted reliability management of SoCs using on-chip clock sweeping and machine learningMehdi Sadi, Gustavo K. Contreras, Dat Tran, Jifeng Chen, LeRoy Winemberg, Mark Tehranipoor. 1-10 [doi]
• Pylon: Towards an integrated customizable volume diagnosis infrastructureYan Pan, Rao Desineni, Kannan Sekar, Atul Chittora, Sherwin Fernandes, Neerja Bawaskar, John M. Carulli. 1-9 [doi]
• An on-chip self-test architecture with test patterns recorded in scan chainsKuen-Jong Lee, Pin-Hao Tang, Michael A. Kochte. 1-10 [doi]
• Using symbolic canceling to improve diagnosis from compacted responseKamran Saleem, Nur A. Touba. 1-7 [doi]
• Putting wasted clock cycles to use: Enhancing fortuitous cell-aware fault detection with scan shift captureFanchen Zhang, Daphne Hwong, Yi Sun, Allison Garcia, Soha Alhelaly, Geoff Shofner, LeRoy Winemberg, Jennifer Dworak. 1-10 [doi]
• A reconfigurable built-in memory self-repair architecture for heterogeneous cores with embedded BIST datapathV. R. Devanathan, Sumant Kale. 1-6 [doi]
• A unified test and fault-tolerant multicast solution for network-on-chip designsDong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara. 1-9 [doi]
• Test time efficient group delay filter characterization technique using a discrete chirped excitation signalPeter Sarson. 1-6 [doi]
• Analog fault coverage improvement using final-test dynamic part average testingWim Dobbelaere, Ronny Vanhooren, Willy De Man, Koen Matthijs, Anthony Coyette, Baris Esen, Georges G. E. Gielen. 1-9 [doi]
• Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer boardToru Nakura, Naoki Terao, Masahiro Ishida, Rimon Ikeno, Takashi Kusaka, Tetsuya Iizuka, Kunihiro Asada. 1-8 [doi]
• Novel crosstalk evaluation method for high-density signal traces using clock waveform conversion techniqueTakayuki Nakamura, Koji Asami. 1-7 [doi]
• SERDES external loopback test using production parametric-test hardwareShalini Arora, Aman Aflaki, Sounil Biswas, Masashi Shimanouchi. 1-7 [doi]
• Supply-voltage optimization to account for process variations in high-volume manufacturing testingGurunath Kadam, Markus Rudack, Krishnendu Chakrabarty, Juergen Alt. 1-9 [doi]
• Efficient cross-layer concurrent error detection in nonlinear control systems using mapped predictive check statesSuvadeep Banerjee, Abhijit Chatterjee, Jacob A. Abraham. 1-10 [doi]
• Online slack-time binning for IO-registered die-to-die interconnectsChih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng. 1-8 [doi]
• Advanced test methodology for complex SoCsPavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian. 1-10 [doi]
• RF test accuracy and capacity enhancement on ATE for silicon TV tunersY. Fan, A. Verma, Y. Su, L. Rose, J. Janney, V. Do, S. Kumar. 1-10 [doi]
• I-Q signal generation techniques for communication IC testing and ATE systemsMasahiro Murakami, Haruo Kobayashi, Shaiful Nizam Bin Mohyar, Osamu Kobayashi, Takahiro Miki, Junya Kojima. 1-10 [doi]
• DE-LOC: Design validation and debugging under limited observation and control, pre- and post-silicon for mixed-signal systemsBarry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee. 1-10 [doi]
• Transformation of multiple fault models to a unified model for ATPG efficiency enhancementCheng-Hung Wu, Kuen-Jong Lee. 1-10 [doi]
• Known-good-die test methods for large, thin, high-power digital devicesDave Armstrong, Gary Maier. 1-6 [doi]
• Test chip design for optimal cell-aware diagnosabilitySoumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. Shawn Blanton. 1-8 [doi]
• Variation and failure characterization through pattern classification of test data from multiple test stagesChun-Kai Hsu, Peter Sarson, Gregor Schatzberger, Friedrich Peter Leisenberger, John M. Carulli Jr., Siddhartha Siddhartha, Kwang-Ting Cheng. 1-10 [doi]
• Low cost ultra-pure sine wave generation with self calibrationYuming Zhuang, Akhilesh Kesavan Unnithan, Arun Joseph, Siva Sudani, Benjamin Magstadt, Degang Chen. 1-9 [doi]
• Automatic test signal generation for mixed-signal integrated circuits using circuit partitioning and interval analysisAnthony Coyette, Baris Esen, Wim Dobbelaere, Ronny Vanhooren, Georges G. E. Gielen. 1-10 [doi]
• Automated measurement of defect tolerance in mixed-signal ICsStephen Sunter, Alessandro Valerio, Riccardo Miglierina. 1-8 [doi]
• Built-in self-test for micro-electrode-dot-array digital microfluidic biochipsZipeng Li, Kelvin Yi-Tse Lai, Po-Hsien Yu, Krishnendu Chakrabarty, Tsung-Yi Ho, Chen-Yi Lee. 1-10 [doi]
• A novel diagnostic test generation methodology and its application in production failure isolationM. Enamul Amyeen, Dongok Kim, Maheshwar Chandrasekar, Mohammad Noman, Srikanth Venkataraman, Anurag Jain, Neha Goel, Ramesh Sharma. 1-10 [doi]
• Recycled FPGA detection using exhaustive LUT path delay characterizationMd Mahbub Alam, Mark Tehranipoor, Domenic Forte. 1-10 [doi]
• Logic characterization vehicle design reflection via layout rewiringPhillip Fynan, Zeye Dexter Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton. 1-10 [doi]
• What we know after twelve years developing and deploying test data analytics solutionsKenneth M. Butler, Amit Nahar, W. Robert Daasch. 1-8 [doi]
• Harnessing process variations for optimizing wafer-level probe-test flowAli Ahmadi, Constantinos Xanthopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris. 1-8 [doi]
• Test point insertion in hybrid test compression/LBIST architecturesElham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada. 1-10 [doi]
• Handling wrong mapping: A new direction towards better diagnosis with low pin convolution compressorsSubhadip Kundu, Parthajit Bhattacharya, Rohit Kapur. 1-7 [doi]
• Testing of interposer-based 2.5D integrated circuitsRan Wang, Krishnendu Chakrabarty. 1-10 [doi]
• Active reliability monitor: Defect level extrinsic reliability monitoring on 22nm POWER8 and zSeries processorsMichael Johnson, Brian Noble, Mark Johnson, Jim Crafts, Cynthia Manya, John Deforge. 1-8 [doi]
• Diagnostic resolution improvement through learning-guided physical failure analysisCarlston Lim, Yang Xue, Xin Li 0001, Ronald D. Blanton, M. Enamul Amyeen. 1-10 [doi]
• Securing digital microfluidic biochips by randomizing checkpointsJack Tang, Ramesh Karri, Mohamed Ibrahim, Krishnendu Chakrabarty. 1-8 [doi]
• Statistical outlier screening as a test solution health monitorDavid Shaw, Dirk Hoops, Kenneth M. Butler, Amit Nahar. 1-10 [doi]
• EMACS: Efficient MBIST architecture for test and characterization of STT-MRAM arraysInsik Yoon, Ashwin Chintaluri, Arijit Raychowdhury. 1-10 [doi]
• Output bit selection methodology for test response compactionWei-Cheng Lien, Kuen-Jong Lee. 1-10 [doi]
• A suite of IEEE 1687 benchmark networksAnton Tsertov, Artur Jutman, Sergei Devadze, Matteo Sonza Reorda, Erik Larsson, Farrokh Ghani Zadegan, Riccardo Cantoro, Mehrdad Montazeri, Rene Krenz-Baath. 1-10 [doi]
• Accurate anomaly detection using correlation-based time-series analysis in a core router systemShi Jin, Zhaobo Zhang, Krishnendu Chakrabarty, Xinli Gu. 1-10 [doi]
• Defect tolerance for CNFET-based SRAMsTianjian Li, Li Jiang, Xiaoyao Liang, Qiang Xu, Krishnendu Chakrabarty. 1-9 [doi]
• Machine learning-based defense against process-aware attacks on Industrial Control SystemsAnastasis Keliris, Hossein Salehghaffari, Brian R. Cairl, Prashanth Krishnamurthy, Michail Maniatakos, Farshad Khorrami. 1-10 [doi]
• Cross-layer system reliability assessment framework for hardware faultsAlessandro Vallero, Alessandro Savino, Gianfranco Politano, S. Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, A. Gonzalez, Maha Kooli, Alberto Bosio, Giorgio Di Natale. 1-10 [doi]
• Memory repair for high fault ratesPanagiota Papavramidou. 1-10 [doi]
• Accessing 1687 systems using arbitrary protocolsMichele Portolan. 1-9 [doi]
• A built-in self-repair scheme for DRAMs with spare rows, columns, and bitsChih-Sheng Hou, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou. 1-7 [doi]
• An accurate algorithm for computing mutation coverage in model checkingHuina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li, Bo Liu. 1-10 [doi]
• Upper-bound computation for optimal retargeting in IEEE1687 networksFarrokh Ghani Zadegan, Rene Krenz-Baath, Erik Larsson. 1-10 [doi]
• Mixed-signal ATE technology and its impact on today's electronic systemGordon W. Roberts. 1-7 [doi]
• Fault simulation for analog test coverageJyotsna Sequeira, Suriyaprakash Natarajan, Prashant Goteti, Nitin Chaudhary. 1-7 [doi]
• Effective DC fault models and testing approach for open defects in analog circuitsBaris Esen, Anthony Coyette, Georges G. E. Gielen, Wim Dobbelaere, Ronny Vanhooren. 1-9 [doi]
• Plenary keynote address Tuesday: The business of test: Test and semiconductor economicsWalden C. Rhines. 9 [doi]
• Keynote address Wednesday: Hardware inference accelerators for machine learningRob A. Rutenbar. 10 [doi]
• Keynote address Thursday: Addressing semiconductor industry needs: Defining the future through creative, exciting researchKen Hansen. 11 [doi]