Table of Contents

• Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan applicationSujit Dey, Miodrag Potkonjak, Rabindra K. Roy. 2-7 [doi]
• On identifying undetectable and redundant faults in synchronous sequential circuitsIrith Pomeranz, Sudhakar M. Reddy. 8-14 [doi]
• Delay-fault testability preservation of the concurrent decomposition and factorization transformationsAiman El-Maleh, Janusz Rajski. 15-21 [doi]
• Design of fully testable circuits by functional decomposition and implicit test pattern generationBernd Steinbach, M. Stockert. 22-27 [doi]
• Retiming sequential circuits to enhance testabilitySujit Dey, Srimat T. Chakradhar. 28-33 [doi]
• A new strategy for testing analog filtersDiego Vázquez, Adoración Rueda, José Luis Huertas. 36-41 [doi]
• A design-for-test technique for switched-capacitor filtersMani Soma, Vladimir Kolarik. 42-47 [doi]
• Design for diagnosability of linear digital filters using time-space expansionAbhijit Chatterjee, Rabindra K. Roy. 48-53 [doi]
• Multifrequency testability analysis for analog circuitsMustapha Slamani, Bozena Kaminska. 54-59 [doi]
• A BIST technique for a frequency response and intermodulation distortion test of a sigma-delta ADCMichael F. Toner, Gordon W. Roberts. 60-65 [doi]
• A design for testability technique for test pattern generation with LFSRsDimitrios Kagaris, Spyros Tragoudas. 68-73 [doi]
• Test embedding with discrete logarithmsMody Lempel, Sandeep K. Gupta, Melvin A. Breuer. 74-80 [doi]
• Multiple weighted cellular automataDanial J. Neebel, Charles R. Kime. 81-86 [doi]
• Structural constraints for circular self-test pathsJoan Carletta, Christos A. Papachristou. 87-92 [doi]
• Aliasing error for a mask ROM built-in self-testKazuhiko Iwasaki, Akinori Furuta, Shigeo Nakamura. 93-98 [doi]
• Discrete test generation by continuous methodsIgor Rivin, Srimat T. Chakradhar. 100-105 [doi]
• ICAT: incremental combinational ATPGByung S. So, Charles R. Kime. 106-113 [doi]
• Test generation and three-state elements, buses, and bidirectionalsJ. Th. van der Linden, Mario H. Konijnenburg, Ad J. Van de Goor. 114-121 [doi]
• Functional learning: a new approach to learning in digital circuitsRajarshi Mukherjee, Jawahar Jain, Dhiraj K. Pradhan. 122-127 [doi]
• Diagnostic simulation of stuck-at faults in combinational circuitsSreejit Chakravarty, Yiming Gong. 128-133 [doi]
• Novel architectures for TSC/CD and SFS/SCD synchronous controllersSayed Mohammad Kia, Sri Parameswaran. 138-143 [doi]
• Controllable self-checking checkers for conditional concurrent checkingSteffen Tarnick. 144-150 [doi]
• Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan designMichael Gössel, Egor S. Sogomonyan. 151-157 [doi]
• Efficient UBIST for RAMsMichael Nicolaidis. 158-166 [doi]
• On-line delay testing of digital circuitsPiero Franco, Edward J. McCluskey. 167-173 [doi]
• Coverage metrics for functional testsJohn R. Wallack, Ramaswami Dandapani. 176-181 [doi]
• On the complexity of terminal stuck-at fault detection tests for monotone Boolean functionsValery A. Vardanian. 182-185 [doi]
• Limitations in predicting defect level based on stuck-at fault coverageJaehong Park, Mark Naivar, Rohit Kapur, M. Ray Mercer, Thomas W. Williams. 186-191 [doi]
• Correlating defect level to final test fault coverage for modular structured designs [microcontroller family]Theo J. Powell, Kenneth M. Butler, Mike Ales, Roy Haley, Mark Perry. 192-196 [doi]
• Quality impacts of non-uniform fault coveragePeter C. Maxwell. 197-200 [doi]
• On compacting test sets by addition and removal of test vectorsSeiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy. 202-207 [doi]
• Neural models for transistor and mixed-level test generationCarolina L. C. Cooper, Michael L. Bushnell. 208-213 [doi]
• A new functional fault model for system-level descriptionsPaolo Camurati, Fulvio Corno, Michela Meo, Paolo Prinetto. 214-219 [doi]
• Sequential test generation with reduced test clocks for partial scan designsSoo-Young Lee, Kewal K. Saluja. 220-225 [doi]
• Speeding up behavioral test pattern generation using an algorithmic improvementLoïc Vandeventer, Jean François Santucci, Norbert Giambiasi. 226-231 [doi]
• A power supply ramping and current measurement based technique for analog fault diagnosisShyam S. Somayajula, Edgar Sánchez-Sinencio, José Pineda de Gyvez. 234-239 [doi]
• Architecture of test support ICs for mixed-signal testingJosé Silva Matos, João Canas Ferreira, Ana C. Leão, J. Machado Silva. 240-246 [doi]
• An organization of the test bus for analog and mixed-signal systemsJanusz A. Starzyk, Zhi-Hong Liu, Jun Zou. 247-251 [doi]
• Designing self-exercising analogue checkersVladimir Kolarik, Marcelo Lubaszewski, Bernard Courtois. 252-257 [doi]
• Analog circuit observer blocksRamesh Harjani, Bapiraju Vinnakota. 258-263 [doi]
• FACTS: fault coverage estimation by test vector samplingKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell. 266-271 [doi]
• New advances in path delay fault testing of combinational circuitsXiaodong Xie, Alexander Albicki. 272-277 [doi]
• Realization of fully path-delay-fault testable non-scan sequential circuitsWuudiann Ke, Premachandran R. Menon. 278-283 [doi]
• On broad-side delay testJacob Savir, Srinivas Patil. 284-290 [doi]
• Weighted random robust path delay testing of synthesized multilevel circuitsWeili Wang, Sandeep K. Gupta. 291-297 [doi]
• Fault models and tests for Ring Address Type FIFOsAd J. Van de Goor, Ivo Schanstra, Yervant Zorian. 300-305 [doi]
• An industrial experience in the built-in self test of embedded RAMsPaolo Camurati, Paolo Prinetto, Matteo Sonza Reorda, Stefano Barbagallo, Andrea Burri, Davide Medina. 306-311 [doi]
• Automating the verification of memory testsAd J. Van de Goor, B. Smit. 312-318 [doi]
• Linear finite state machine for lD ILAsMurali M. R. Gala, Peter Utama, Don E. Ross, Karan L. Watson. 325-332 [doi]
• Functional design verification for the PowerPC 601 microprocessorS. Glenn, G. Meil, E. Rodriguez, J. Brooks. 334-339 [doi]
• Fault probabilities in routing channels of VLSI standard cell designsG. Spiegel. 340-347 [doi]
• On robustness of required random test length with regard to fault occurrence hypothesesS. Crepaux-Motte, Mireille Jacomino, Rene David. 348-355 [doi]
• Known-good-die technologies on the horizonBarbara Vasquez, Don R. Van Overloop, Scott E. Lindsey. 356-359 [doi]
• Analyzing the design-for-test techniques in a multiple substrate MCMJoel A. Jorgenson, Russell J. Wagner. 360-365 [doi]
• DDQ detectable bridges in combinational CMOS circuitsEugeni Isern, Joan Figueras. 368-373 [doi]
• Incorporating IDDQ testing in BIST: improved coverage through test diversityAdit D. Singh, Jason P. Hurst. 374-379 [doi]
• DDQ-testing in parallel testable FAST-SRAMsChristian Elm, Djamshid Tavangarian. 380-385 [doi]
• Circuit-level dictionaries of CMOS bridging faultsTerry Lee, Weitong Chuang, Ibrahim N. Hajj, W. Kent Fuchs. 386-391 [doi]
• CMOS bridging fault modelingMichel Renovell, P. Huc, Yves Bertrand. 392-397 [doi]
• Eliminating undetectable shorts between horizontal wires during channel routingRichard McGowen, F. Joel Ferguson. 402-407 [doi]
• Design for testability of on-line multipliersHakim Bederr, Michael Nicolaidis, Alain Guyot. 408-414 [doi]
• Boundary-scan: beyond production testRichard M. Sedmark. 415-420 [doi]
• A new high level testability measure: description and evaluationM.-H. Gentil, Didier Crestani, Abdennour El Rhalibi, C. Durante. 421-426 [doi]
• Impact of behavioral modifications for testabilityThomas Thomas, Praveen Vishakantaiah, Jacob A. Abraham. 427-432 [doi]
• Open faults in BiCMOS gatesSiyad C. Ma, Edward J. McCluskey. 434-439 [doi]
• Gate-to-channel shorts in BiCMOS logic gatesC. J. Chen, Samiha Mourad. 440-445 [doi]
• On evaluating competing bridge fault models for CMOS ICsBrian Chess, Carl Roth, Tracy Larrabee. 446-451 [doi]
• Three-pattern tests for delay faultsPiero Franco, Edward J. McCluskey. 452-456 [doi]
• Input pattern classification for transistor level testing of BiCMOS circuitsSankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya. 457-462 [doi]