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    Journal: IEEE Design & Test of Computers

    Volume 19, Issue 6

    0 -- 0Peter J. Ashenden. Standards: Technical activities in Accellera
    3 -- 0Rajesh Gupta. EIC Message: The Neglected Community
    4 -- 5Grant Martin. Guest Editor s Introduction: The Reuse of Complex Architectures
    6 -- 16Andrew Mihal, Chidamber Kulkarni, Matthew W. Moskewicz, Mel M. Tsai, Niraj Shah, Scott J. Weber, Yujia Jin, Kurt Keutzer, Christian Sauer, Kees A. Vissers, Sharad Malik. Developing Architectural Platforms: A Disciplined Approach
    17 -- 26Pierre G. Paulin, Chuck Pilkington, Essaid Bensoudane. StepNP: A System-Level Exploration Platform for Network Processors
    27 -- 35Clifford Liem, Francois Breant, Sarveta Jadhav, Ray O Farrell, Ray Ryan, Oz Levia. Embedded Tools for a Configurable and Customizable DSP Architecture
    36 -- 43Greg Stitt, Frank Vahid. Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic
    44 -- 51Vincent John Mooney III, Douglas M. Blough. A Hardware-Software Real-Time Operating System Framework for SoCs
    52 -- 63Wander O. Cesário, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed Amine Jerraya, Lovic Gauthier, Mario Diaz-Nava. Multiprocessor SoC Platforms: A Component-Based Design Approach
    64 -- 72Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas. Practical Oscillation-Based Test of Integrated Filters
    73 -- 82Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José Luis Huertas. Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macrocell
    83 -- 89Michel Renovell, Florence Azaïs, Yves Bertrand. Improving Defect Detection in Static-Voltage Testing
    90 -- 100Amit Chowdhary, Rajesh K. Gupta. A Methodology for Synthesis of Data Path Circuitse
    101 -- 0. Conference Reports
    102 -- 103. Panel Summaries
    104 -- 105Andrew B. Kahng. The Road Ahead: The significance of packaging
    108 -- 109. TTTC Newsletter
    110 -- 119. Annual Index
    120 -- 0. The Last Byte

    Volume 19, Issue 5

    0 -- 0Krishnendu Chakrabarty, Erik Jan Marinissen. How Useful are the ITC 02 SoC Test Benchmarks?
    1 -- 0Rajesh Gupta. Sustaining an Industry Obsession
    5 -- 7Jaume Segura, Peter C. Maxwell. Guest Editors Introduction: Defect-Oriented Testing in the Deep-Submicron Era
    8 -- 16Sagar S. Sabade, D. M. H. Walker. IDDQ Test: Will It Survive the DSM Challenge?
    18 -- 26Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez. Resistance Characterization for Weak Open Defects
    27 -- 35Xavier Aragonès, José Luis González, Francesc Moll, Antonio Rubio. Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
    36 -- 43Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins. Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits
    44 -- 52Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich. High Defect Coverage with Low-Power Test Sequences in a BIST Environment
    54 -- 55Robert C. Aitken, Donald L. Wheater. Guest Editors Introduction: Stressing the Fundamentals
    56 -- 64Shuo Sheng, Michael S. Hsiao. Efficient Sequential Test Generation Based on Logic Simulation
    65 -- 72Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera. Extending OPMISR beyond 10x Scan Test Efficiency
    74 -- 81W. Robert Daasch, James McNames, Robert Madge, Kevin Cota. Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort
    82 -- 91Sule Ozev, Christian Olgaard, Alex Orailoglu. Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers
    92 -- 104Marcello Dalpasso, Alessandro Bogliolo, Luca Benini. Virtual Simulation of Distributed IP-Based Designs
    114 -- 115. Conference Reports
    116 -- 117. Test Technology TC Newsletter
    118 -- 0. Design Automation Technical Committee Newsletter

    Volume 19, Issue 4

    3 -- 0. Building a community
    5 -- 6Peter Marwedel. Guest Editor s Introduction: Processor-Based Designs
    7 -- 17Dongkun Shin, Hojun Shim, Yongsoo Joo, Han-Saem Yun, Jihong Kim, Naehyuck Chang. Energy-Monitoring Tool for Low-Power Embedded Programs
    18 -- 27Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey. Embedded Software-Based Self-Test for Programmable Core-Based Designs
    28 -- 38Ing-Jer Huang, Chung-Fu Kao, Hsin-Ming Chen, Ching-Nan Juan, Tai-An Lu. A Retargetable Embedded In-Circuit Emulation Module for Microprocessors
    39 -- 50Martijn J. Rutten, Jos T. J. van Eijndhoven, Egbert G. T. Jaspers, Pieter van der Wolf, Evert-Jan D. Pol, Om Prakash Gangwal, Adwin H. Timmer. A Heterogeneous Multiprocessor Architecture for Flexible Media Processing
    51 -- 58Rainer Leupers. Compiler Design Issues for Embedded Processors
    59 -- 69Pierre G. Paulin, Miguel Santana. FlexWare: A Retargetable Embedded-Software Development Environment
    72 -- 73David Blaauw, Luciano Lavagno. Guest Editors Introduction: Hot Topics at This Year s Design Automation Conference
    74 -- 83Michael H. Perrott. Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL Circuits
    84 -- 95Robert Siegmund, Dietmar Müller. Automatic Synthesis of Communication Controller Hardware from Protocol Specifications
    96 -- 106Kanna Shimizu, David L. Dill. Using Formal Specifications for Functional Validation of Hardware Designs
    107 -- 117Alex Kondratyev, Kelvin Lwin. Design of Asynchronous Circuits Using Synchronous CAD Tools
    118 -- 130Kanishka Lahiri, Sujit Dey, Anand Raghunathan. Communication-Based Power Management
    131 -- 132Aarti Gupta. Assertion-based verification turns the corner

    Volume 19, Issue 3

    0 -- 0Andrew B. Kahng. Variability
    1 -- 0. Enabling IP
    5 -- 7. Guest Editor s Introduction: What is Infrastructure IP?
    8 -- 13Teresa L. McLaurin, Souvik Ghosh. ETM10 Incorporates Hardware Segment of IEEE P1500
    14 -- 23Jim Bordelon, Ben Tranchina, Vipin Madangarli, Mark Craig. A Strategy for Mixed-Signal Yield Improvement
    24 -- 36Sassan Tabatabaei, André Ivanov. Embedded Timing Analysis: A SoC Infrastructure
    37 -- 45Bart Vermeulen, Sandeep Kumar Goel. Design for Debug: Catching Design Errors in Digital Chips
    46 -- 55Stephen Pateras. IP for Embedded Diagnosis
    56 -- 70Eric Dupont, Michael Nicolaidis, Peter Rohr. Embedded Robustness IPs for Transient-Error-Free ICs
    72 -- 81Andrew E. Caldwell, Igor L. Markov. Toward CAD-IP Reuse: A Web Bookshelf of Fundamental Algorithms
    82 -- 92Patrick Girard. Survey of Low-Power Testing of VLSI Circuits
    94 -- 105Alfredo Benso, Silvia Chiusano, Paolo Prinetto. DFT and BIST of a Multichip Module for High-Energy Physics Experiments
    106 -- 113. Design and Test Education in Latin America
    114 -- 115Peter J. Ashenden. What Makes a Good Standard?
    116 -- 0Adam Osseiran. Conference Reports
    117 -- 0. DATC Newsletter
    118 -- 119. TTTC Newsletter

    Volume 19, Issue 2

    3 -- 0. Deep-Submicron Challenges
    4 -- 15Luis Miguel Silveira, Nuno Vargas. Characterizing Substrate Coupling in Deep-Submicron Designs
    16 -- 23Michele Favalli, Cecilia Metra. Online Testing Approach for Very Deep-Submicron ICs
    24 -- 33Zhanping Chen, Liqiong Wei, Ali Keshavarzi, Kaushik Roy. IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions
    34 -- 43Mircea R. Stan. CMOS Circuits with Subvolt Supply Voltages
    44 -- 48Chenn-Jung Huang, Chua-Chin Wang, Chi-Feng Wu. Image Processing Techniques for Wafer Defect Cluster Identification
    50 -- 58Carlos Galup-Montoro, Márcio C. Schneider, Rafael M. Coitinho. Resizing Rules for MOS Analog-Design Reuse
    60 -- 69Stephan Schulz II, Jerzy W. Rozenblit, Klaus Buchenrieder. Multilevel Testing for Design Verification of Embedded Systems
    70 -- 71. Shared Red Bricks
    72 -- 73. Standards
    74 -- 76. Panel Summaries
    77 -- 0. DATC Newsletter
    78 -- 79. TTTC Newsletter
    80 -- 0. Yet Another Thiotimoline Application

    Volume 19, Issue 1

    1 -- 0. EIC Message
    5 -- 0. News
    6 -- 17Markus Rudack, Michael Redeker, Jörg Hilgenstock, Sören Moch, Jens Castagne. A Large-Area Integrated Multiprocessor System for Video Applications
    18 -- 28Chouki Aktouf. A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
    29 -- 41Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly. Modeling the Economics of Testing: A DFT Perspective
    42 -- 53Ismet Bayraktaroglu, Alex Orailoglu. Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST
    54 -- 64Jun Zhao, Fred J. Meyer, Fabrizio Lombardi. Analyzing and Diagnosing Interconnect Faults in Bus-Structured Systems
    66 -- 74Yi Cai, Bernd Laquai, Kent Luehman. Jitter Testing for Gigabit Serial Communication Transceivers
    76 -- 83Philippe Magarshack. Improving SoC Design Quality through a Reproducible Design Flow
    84 -- 85. Verilog and Other Standards
    86 -- 87. Conference Reports
    88 -- 90. Panel Summaries
    91 -- 0. New Products
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