| 683 | -- | 684 | Yehea I. Ismail, Byron Krauter. Guest editorial: special issue on on-chip inductance in high-speed integrated circuits |
| 685 | -- | 694 | Yehea I. Ismail. On-chip inductance cons and pros |
| 695 | -- | 711 | Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, Barry J. Rubin, H. H. Smith. A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis |
| 712 | -- | 729 | Michael W. Beattie, Lawrence T. Pileggi. On-chip induction modeling: basics and advanced methods |
| 730 | -- | 745 | Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi. Inductance model and analysis methodology for high-speed on-chip interconnect |
| 746 | -- | 761 | Haitian Hu, Sachin S. Sapatnekar. Efficient inductance extraction using circuit-aware techniques |
| 762 | -- | 776 | Andrey V. Mezhiba, Eby G. Friedman. Inductive properties of high-performance power distribution grids |
| 777 | -- | 788 | C. Svensson. Electrical interconnects revitalized |
| 789 | -- | 798 | Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White. Managing on-chip inductive effects |
| 799 | -- | 805 | Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu. Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion |
| 806 | -- | 823 | Massimo Alioto, Gaetano Palumbo. Analysis and comparison on full adder block in submicron technology |
| 824 | -- | 835 | Stelian Alupoaei, Srinivas Katkoori. Net-based force-directed macrocell placement for wirelength optimization |
| 836 | -- | 843 | Chunhong Chen, Jiang Zhao, Majid Ahmadi. Probability-based approach to rectilinear Steiner tree problems |
| 844 | -- | 855 | D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. A clock power model to evaluate impact of architectural and technology optimizations |
| 856 | -- | 863 | Tony Givargis, Frank Vahid, Jörg Henkel. Instruction-based system-level power evaluation of system-on-a-chip peripheral cores |
| 864 | -- | 875 | Ramesh Karri, Kaijie Wu. Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique |
| 876 | -- | 885 | Kamal S. Khouri, Niraj K. Jha. Leakage power analysis and reduction during behavioral synthesis |
| 886 | -- | 901 | Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang. Arbitrarily shaped rectilinear module placement using the transitive closure graph representation |
| 902 | -- | 912 | Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi. Area-efficient high-speed decoding schemes for turbo decoders |
| 913 | -- | 918 | Wai Chung, T. Lo, M. Sachdev. A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops |
| 919 | -- | 923 | Farzan Fallah, Pranav Ashar, Srinivas Devadas. Functional vector generation for sequential HDL models under an observability-based code coverage metric |
| 924 | -- | 929 | Jer Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen. Design of a dynamic pipelined architecture for fuzzy color correction |
| 929 | -- | 934 | Rung-Bin Lin, Chi-Ming Tsai. Theoretical analysis of bus-invert coding |
| 935 | -- | 942 | Peter Oehler, Christoph Grimm, Klaus Waldschmidt. A methodology for system-level synthesis of mixed-signal applications |
| 942 | -- | 949 | Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn. ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits |