Michalis D. Galanis - researchr alias

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Viewing Publication 1 - 59 from 59

2009

Compiler assisted architectural exploration framework for coarse grained reconfigurable arraysGrigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis. tjs, 48(2):115-151, 2009. [doi]

Resource aware mapping on coarse grained reconfigurable arraysGrigoris Dimitroulakos, Stavros Georgiopoulos, Michalis D. Galanis, Costas E. Goutis. mam, 33(2):91-105, 2009. [doi]

2008

Speedups from extending embedded processors with a high-performance coarse-grained reconfigurable data-pathMichalis D. Galanis, Costas E. Goutis. jsa, 54(5):479-490, 2008. [doi]

Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-PathMichalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis. vlsisp, 50(2):179-200, 2008. [doi]

Novel Hardware Implementation of the Cipher Message Authentication CodeHarris E. Michail, Georgios N. Selimis, Michalis D. Galanis, Dimitrios M. Schinianakis, Constantinos E. Goutis. jcnc, 2008, 2008. [doi]

2007

Design space exploration of an optimized compiler approach for a generic reconfigurable array architectureGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis. tjs, 40(2):127-157, 2007. [doi]

Compiler assisted architectural exploration for coarse grained reconfigurable arraysGrigoris Dimitroulakos, Nikos Kostaras, Michalis D. Galanis, Costas E. Goutis. glvlsi 2007: 164-167 [doi]

A unified evaluation framework for coarse grained reconfigurable array architecturesGrigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis. cf 2007: 161-172 [doi]

Exploring the speedups of embedded microprocessor systems utilizing a high-performance coprocessor data-pathMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. tjs, 39(3):251-271, 2007. [doi]

Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-pathMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. glvlsi 2007: 2-7 [doi]

Speedups and Energy Savings of Microprocessor Platforms with a Coarse-Grained Reconfigurable Data-PathMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. ipps 2007: 1-8 [doi]

Performance Optimization of Embedded Applications in a Hybrid Reconfigurable PlatformMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. patmos 2007: 352-362 [doi]

Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable SystemMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. tvlsi, 15(12):1362-1366, 2007. [doi]

Automated framework for partitioning DSP applications in hybrid reconfigurable platformsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. mam, 31(1):1-14, 2007. [doi]

Speedups in embedded systems with a high-performance coprocessor datapathMichalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis. todaes, 12(3), 2007. [doi]

2006

Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architecturesGrigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis. ipps 2006: [doi]

Resource constrained modulo scheduling for coarse-grained reconfigurable arraysGrigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis. iscas 2006: [doi]

Performance Improvements from Partitioning Applications to FPGA Hardware in Embedded SoCsMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. tjs, 35(2):185-199, 2006. [doi]

Mapping DSP applications on processor/coarse-grain reconfigurable array architecturesMichalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis. iscas 2006: [doi]

Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logicMichalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis. ipps 2006: [doi]

Mapping DSP applications on processor systems with coarse-grain reconfigurable hardwareMichalis D. Galanis, Grigoris Dimitroulakos, Constantinos E. Goutis. ipps 2006: [doi]

Partitioning Methodology for Heterogeneous Reconfigurable Functional UnitsMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. tjs, 38(1):17-34, 2006. [doi]

Performance Improvements in Microprocessor Systems Utilizing a Copressor Data-PathMichalis D. Galanis, Gregory Dimitroulakos, Costas E. Goutis. samos 2006: 85-92 [doi]

A high-performance data path for synthesizing DSP kernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis. tcad, 25(6):1154-1162, 2006. [doi]

A design flow for speeding-up dsp applications in heterogeneous reconfigurable systemsMichalis D. Galanis, Athanasios Milidonis, Athanasios Kakarountas, Costas E. Goutis. mj, 37(6):554-564, 2006. [doi]

Architectures and FPGA Implementations of the 64-Bit MISTY1 Block CipherParis Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou. jcsc, 15(6):817-831, 2006. [doi]

2005

Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable ArraysGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis. asap 2005: 161-168 [doi]

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000Grigoris Dimitroulakos, Michalis D. Galanis, Athanasios Milidonis, Constantinos E. Goutis. integration, 39(1):1-11, 2005. [doi]

A Compiler Method for Memory-Conscious Mapping of Applications on Coarse-Grained Reconfigurable ArchitecturesGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis. ipps 2005: [doi]

Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCsGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis. fpl 2005: 630-635

A high-throughput and memory efficient 2D discrete wavelet transform hardware architecture for JPEG2000 standardGrigoris Dimitroulakos, Michalis D. Galanis, Costas E. Goutis, Athanasios Milidonis. iscas 2005: 472-475 [doi]

Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable HardwareMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. asap 2005: 50-59 [doi]

Accelerating Applications by Mapping Critical Kernels on Coarse-Grain Reconfigurable Hardware in Hybrid SystemsMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. fccm 2005: 301-302 [doi]

Performance Gains from Partitioning Embedded Applications in Processor-FPGA SoCsMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. patmos 2005: 247-256 [doi]

An automated methodology for memory-conscious mapping of DSP applications on coarse-grain reconfigurable arraysMichalis D. Galanis, Gregory Dimitroulakos, Constantinos E. Goutis. iscas 2005: 3519-3522 [doi]

Partitioning DSP applications to different granularity reconfigurable hardwareMichalis D. Galanis, Grigoris Dimitroulakos, Costas E. Goutis. icecsys 2005: 1-4 [doi]

A method for partitioning applications in hybrid reconfigurable architecturesMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Costas E. Goutis. dafes, 10(1):27-47, 2005. [doi]

A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable PlatformsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. ipps 2005: [doi]

A methodology for partitioning DSP applications in hybrid reconfigurable systemsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. iscas 2005: 1206-1209 [doi]

A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive KernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis. jcsc, 14(4):877-893, 2005. [doi]

Comparison of the Hardware Implementation of Stream CiphersMichalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Constantinos E. Goutis. iajit, 2(4):267-274, 2005. [doi]

A RAM-based FPGA implementation of the 64-bit MISTY1 block cipherParis Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou. iscas 2005: 4641-4644 [doi]

An Fpga Implementation of the Gprs Encryption Algorithm 3 (gea3)Paris Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou. jcsc, 14(2):217-232, 2005. [doi]

2004

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable PlatformsMichalis D. Galanis, Athanasios Milidonis, George Theodoridis, Dimitrios Soudris, Constantinos E. Goutis. date 2004: 247-252 [doi]

A high performance data-path to accelerate DSP kernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis. icecsys 2004: 495-498 [doi]

A novel coarse-grain reconfigurable data-path for accelerating DSP kernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. fpga 2004: 252 [doi]

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-PathMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. patmos 2004: 652-661 [doi]

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-PathMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. fpl 2004: 868-873 [doi]

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-PathMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis. fccm 2004: 275-276 [doi]

A Novel Data-Path for Accelerating DSP KernelsMichalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis. samos 2004: 363-372 [doi]

Comparison of the hardware architectures and FPGA implementations of stream ciphersMichalis D. Galanis, Paris Kitsos, Giorgos Kostopoulos, Nicolas Sklavos, Odysseas G. Koufopavlou, Costas E. Goutis. icecsys 2004: 571-574 [doi]

High-speed hardware implementations of the KASUMI block cipherParis Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou. iscas 2004: 549-552

Architectures and Hardware Implementations of the 64-bit MISTY1 Block CipherParis Kitsos, Michalis D. Galanis, Odysseas G. Koufopavlou. iacr, 2004:140, 2004. [doi]

64-bit Block ciphers: hardware implementations and comparison analysisParis Kitsos, Nicolas Sklavos, Michalis D. Galanis, Odysseas G. Koufopavlou. cee, 30(8):593-604, 2004. [doi]

An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive ApplicationsAthanasios Milidonis, Grigoris Dimitroulakos, Michalis D. Galanis, George Theodoridis, Constantinos E. Goutis, Francky Catthoor. scopes 2004: 122-136 [doi]

A Framework for Data Partitioning for C++ Data-Intensive ApplicationsAthanasios Milidonis, Gregory Dimitroulakos, Michalis D. Galanis, Athanasios P. Kakarountas, George Theodoridis, Constantinos E. Goutis, Francky Catthoor. dafes, 9(2):101-121, 2004. [doi]

2003

Power aware data type refinement on the HIPERLAN/2Gregory Dimitroulakos, Athanasios Milidonis, Michalis D. Galanis, George Theodoridis, Costas E. Goutis, Francky Catthoor. icecsys 2003: 216-219 [doi]

2002

A DSP course for real-time systems design and implementation based on the TMS320C6211 DSKMichalis D. Galanis, Arhanassios Papazacharias, Evangelos Zigouris. icdsp 2002: 853-856 [doi]

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