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Viewing Publication 1 - 48 from 48

2018

A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiencyFangyu Mao, Yan Lu 0002, Seng-Pan U., Rui P. Martins. isscc 2018: 140-142 [doi]

2013

2012

A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizerTao He, Yang Jiang, Yun Du, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2012: 65-68 [doi]

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC techniqueRui Wang, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins. esscirc 2012: 265-268 [doi]

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DACHe Gong Wei, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. jssc, 47(11):2763-2772, 2012. [doi]

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADCSi-Seng Wong, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. cicc 2012: 1-4 [doi]

2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOSGuohe Yin, He Gong Wei, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Zhihua Wang, Rui Paulo Martins. esscirc 2012: 377-380 [doi]

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset CancellationYan Zhu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. jssc, 47(11):2614-2626, 2012. [doi]

2011

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibrationU. Fat Chio, Chi-Hang Chan, Hou-Lon Choi, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. esscirc 2011: 363-366 [doi]

2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOSHe Gong Wei, Chi-Hang Chan, U-Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. isscc 2011: 188-190 [doi]

2010

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADCU-Fat Chio, He Gong Wei, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. tcas, 57-II(8):607-611, 2010. [doi]

An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCsLi Ding, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. apccas 2010: 208-211 [doi]

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulatorsYang Jiang, Kim-Fai Wong, Chen-Yan Cai, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. icecsys 2010: 547-550 [doi]

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOSHe Gong Wei, U-Fat Chio, Yan Zhu, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. tcas, 57-II(1):16-20, 2010. [doi]

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applicationsGuohe Yin, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Zhihua Wang. icecsys 2010: 878-881 [doi]

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOSYan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, Franco Maloberti. jssc, 45(6):1111-1121, 2010. [doi]

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCsYan Zhu, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. vlsi, 2010, 2010. [doi]

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCsYan Zhu, Chi-Hang Chan, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2010: 4061-4064 [doi]

2008

A power-efficient capacitor structure for high-speed charge recycling SAR ADCsYan Zhu 0001, U. Fat Chio, He Gong Wei, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. icecsys 2008: 642-645 [doi]

On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN SystemsPui-In Mak, Seng-Pan U., Rui Paulo Martins. tcas, 55-I(2):496-509, 2008. [doi]

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-OpampsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. tcas, 55-I(8):2188-2201, 2008. [doi]

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth MismatchSai-Weng Sin, U-Fat Chio, Seng-Pan U., Rui Paulo Martins. tcas, 55-II(7):648-652, 2008. [doi]

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifierHe Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2008: 5-8 [doi]

2007

A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADCWeng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins. iscas 2007: 1947-1950 [doi]

2006

A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracyKin-Sang Chio, Seng-Pan U., Rui Paulo Martins. iscas 2006: [doi]

A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement TechniqueKa-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins. apccas 2006: 183-186 [doi]

A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonatorChon-In Lao, Seng-Pan U., Rui Paulo Martins. iscas 2006: [doi]

A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applicationsJun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2006: [doi]

Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receiversPui-In Mak, Seng-Pan U., Rui Paulo Martins. iscas 2006: [doi]

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuitsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2006: [doi]

2005

A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMAKin-Sang Chio, Seng-Pan U., Rui Paulo Martins. iscas 2005: 3099-3102 [doi]

A frequency up-conversion and two-step channel selection embedded CMOS D/A interfaceKa-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins. iscas 2005: 392-395 [doi]

A novel semi-MASH sub-stage for high-order cascade sigma-delta modulatorsChon-In Lao, Seng-Pan U., Rui Paulo Martins. iscas 2005: 3095-3098 [doi]

A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuitsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2005: 1585-1588 [doi]

A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuitsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2005: 1581-1584 [doi]

2004

A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systemsPui-In Mak, Man-Chung Wong, Seng-Pan U.. iscas 2004: 948-951

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiverPui-In Mak, Kin-Kwan Ma, Weng-leng Mok, Chi-sam Sou, Kit-man Ho, Cheng-Man Ng, Seng-Pan U., Rui Paulo Martins. iscas 2004: 1068-1071

A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applicationsPui-In Mak, Seng-Pan U., Rui Paulo Martins. iscas 2004: 417-420

A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systemsSai-Weng Sin, Seng-Pan U., Rui Paulo Martins. iscas 2004: 369-372

Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effectsSeng-Pan U., Sai-Weng Sin, Rui Paulo Martins. tim, 53(4):1279-1288, 2004. [doi]

2003

A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-samplingChon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins. iscas 2003: 1061-1064 [doi]

Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding outputSai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca. iscas 2003: 129-132 [doi]

2001

A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systemsSeng-Pan U., Rui Paulo Martins, José E. Franca. iscas 2001: 320-323 [doi]

High-frequency low-power multirate SC realizations for NTSC/PAL digital video filteringSeng-Pan U., Rui Paulo Martins, José E. Franca. iscas 2001: 204-207 [doi]

1999

Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivitySeng-Pan U., Rui Paulo Martins, José E. Franca. iscas 1999: 57-60 [doi]

High performance multirate SC circuits with predictive correlated double sampling techniqueSeng-Pan U., Rui Paulo Martins, José E. Franca. iscas 1999: 77-80 [doi]

1996

New impulse sampled IIR switched-capacitor interpolatorsSeng-Pan U., Rui Paulo Martins, José E. Franca. icecsys 1996: 203-206 [doi]

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