Abstract is missing.
- Welcome to ASICON 2011Ting-Ao Tang. [doi]
- A behavior-based reconfigurable cache for the low-power embedded processorJiongyao Ye, Jiannan Jin, Takahiro Watanabe. 1-5 [doi]
- A novel method for storage architecture of pipeline FFT processorTing Zhang, Lan Chen, Yan Feng. 6-8 [doi]
- Design of resistant DPA three-valued counter based on SABLYuejun Zhang, Pengjun Wang, Lipeng Hao. 9-12 [doi]
- Improvement of adiabatic domino circuits and its application in multi-valued circuitsQiankun Yang, Pengjun Wang, Fengna Mei. 13-16 [doi]
- Low power shift registers for megabits CMOS image sensorsJinn-Shyan Wang, Tsung-Han Hsieh, Keng-Jui Chang, Chingwei Yeh. 17-20 [doi]
- High-parallel LDPC decoder with power gating designYing Cui, Xiao Peng, Yu Jin, Peilin Liu, Shinji Kimura, Satoshi Goto. 21-24 [doi]
- A reconfigurable macro-pipelined DCT/IDCT acceleratorWenqi Bao, Jiang Jiang, Qing Sun, Yuzhuo Fu. 25-28 [doi]
- Scheduling to timing optimization for a novel high-level synthesis approachLing Li, Teng Wang, Ziyi Hu, Xin'an Wang, Xu Zhang. 29-32 [doi]
- High reliable digital signal processor for automotive applicationYimiao Zhao, Zhigang Ni. 33-34 [doi]
- A novel Differential fault analysis on AES-128Pengjun Wang, Lipeng Hao. 35-38 [doi]
- Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPUMinh Thien Trieu, Huong Thien Hoang, Phong The Vo, Hung Bao Vo, Yoichi Yuyama. 39-42 [doi]
- A hardware/software co-design approach for multiple-standard video bitstream parsingSha Shen, Huibo Zhong, Yibo Fan, Xiaoyang Zeng. 43-46 [doi]
- ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designsJinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang. 47-50 [doi]
- Analysis of adaptive support-weight based stereo matching for hardware realizationJunbao Liu, Shuai Wang, Yang Li, Jun Han, Xiaoyang Zeng. 51-54 [doi]
- A high performance sound source localization system based on macro-pipelined architectureQing Sun, Yuzhuo Fu, Wenqi Bao, Jiang Jiang. 55-58 [doi]
- Research on design of a reconfigurable parallel structure targeted at LFSRWei Li, Xuan Yang, Zibin Dai. 59-63 [doi]
- Using NOC technology to improve photoelectric encoder system for LAMOST spectroscopesZhongyi Han, Jianing Wang, Yizhong Zeng, Zhongwen Hu. 64-66 [doi]
- A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chainZhidong Mao, Liguang Chen, Yuan Wang, Jinmei Lai. 67-70 [doi]
- A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoderTuan Minh Phan Ho, Thang Minh Le, Khanh Duy Vu, Seiji Mochizuki, Kenichi Iwata, Keisuke Matsumoto, Hiroshi Ueda. 71-74 [doi]
- A two-way parallel CAVLC encoder for 4K×2K H.264/AVCHuibo Zhong, Sha Shen, Yibo Fan, Xiaoyang Zeng. 75-78 [doi]
- Multi-stage power gating based on controlling values of logic gatesYu Jin, Shinji Kimura. 79-82 [doi]
- A high speed reconfigurable face detection architectureWeina Zhou, Yao Zou, Lin Dai, Xiaoyang Zeng. 83-86 [doi]
- A coarse-grained reconfigurable computing unitKanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong. 87-90 [doi]
- Battery state of charge estimation using adaptive subspace identification methodSahana Swarup, Sheldon X.-D. Tan, Zao Liu, Hai Wang, Zhigang Hao, Guoyong Shi. 91-94 [doi]
- A new frequency compensation scheme for current-mode DC/DC converterJiake Wang, Jinguang Jiang, Shanshan Li, Xu Gong, Xifeng Zhou, Qingyun Li. 95-99 [doi]
- A high-performance PWM controller with adjustable current limitZe-kun Zhou, Huifang Wang, Yue Shi, Xin-ming, Bo Zhang. 100-103 [doi]
- Capacitor-free, fast transient response CMOS low-dropout regulator with multiple-loop controlXiao Tang, Lenian He. 104-107 [doi]
- A high efficiency current mode step-up/step-down DC-DC converter with smooth transitionYanzhao Ma, Jun Cheng, Guican Chen. 108-111 [doi]
- A non-rectifier wireless power transmission system using on-chip inductorYimeng Zhang, Mengshu Huang, Tsutomu Yoshihara. 112-115 [doi]
- An overview of charge pumping circuits for flash memory applicationsOi-Ying Wong, Hei Wong, Wing-Shan Tam, Chi-Wah Kok. 116-119 [doi]
- Class-AB CMOS buffer with floating class-AB controlPeng Zhang, Fan Ye, Junyan Ren. 120-123 [doi]
- A new topology for fully differential amplifiers that enhances their tolerance to external disturbancesGuoyuan Fu, H. Alan Mantooth, Jia Di. 124-127 [doi]
- Double charge pump circuit with triple charge sharing clock schemeMengshu Huang, Yimeng Zhang, Hao Zhang, Tsutomu Yoshihara. 128-132 [doi]
- CMOS charge pump with separated charge sharing for improved boosting ratio and relaxed timing restrictionSeung-Jae Choi, Young-Hyun Jun, Bai-Sun Kong. 133-136 [doi]
- ROIC with adaptive reset control for improving dynamic range of IR FPAsDoo Hyung Woo, Ilku Nam, Joonwoo Choi. 137-140 [doi]
- A signal conditioner IC for inductive proximity sensorsWengang Huang, Chenghe Wang, Luncai Liu, Xiaozong Huang, Guoqiang Wang. 141-144 [doi]
- A low-power low-noise amplifier for EEG/ECG signal recording applicationsJinghao Feng, Na Yan, Hao Min. 145-148 [doi]
- A TIA-based interface for MEMS capacitive gyroscopeTao Yin, Huanming Wu, Qisong Wu, Haigang Yang, Jiwei Jiao. 149-152 [doi]
- A multi-level arbitration and topology free streaming network for chip multiprocessorJian Wang, Andreas Karlsson, Joar Sohl, Magnus Pettersson, Dake Liu. 153-158 [doi]
- Design and verification of an application-specific PLD using VHDL and SystemVerilogJae-Jin Lee, Young-Jin Oh, Gi-Yong Song. 159-162 [doi]
- Evaluation of deflection routing on various NoC topologiesChaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang. 163-166 [doi]
- ASIC implementation of an OFDM baseband transceiver for HINOCHongming Chen, Xiaoyuan Chen, Tie Liu, Yuhua Cheng. 167-170 [doi]
- Design of four-transistor Pixel for high speed CMOS imageYangfan Zhou, Zhongxiang Cao, Quanliang Li, Qi Qin, Nanjian Wu. 171-174 [doi]
- A Network-on-Chip simulation framework for homogeneous Multi-Processor System-on-ChipYuan Wen Hau, Muhammad N. Marsono, Chia Yee Ooi, Mohamed Khalil Hani. 175-179 [doi]
- Design of a signal processing circuit for quartz crystal microbalance biosensorsShih-Chang Chang, I-Jen Chao, Bin-Da Liu, Chun-Yueh Huang, Mei-Hwa Lee, Hung-Yin Lin. 180-183 [doi]
- A low-power 433MHz transmitter for battery-less Tire Pressure Monitoring SystemJinyu Zhu, Liji Wu, Xiangmin Zhang, Chen Jia, Chun Zhang. 184-187 [doi]
- A high performance and low cost video processing SoC for digital HDTV systemsLongjun Liu, Hongbin Sun, Wenzhe Zhao, Zuoxun Hou, Jingmin Xin, Nanning Zheng. 188-191 [doi]
- A novel hardware prefetching scheme exploiting 2-D spatial locality in multimedia applicationsJin Huang, Jing Xie, Zhigang Mao. 192-195 [doi]
- A NoC-based multi-core architecture for IEEE 802.11i CCMPYang Li, Jun Han, Shuai Wang, Junbao Liu, Xiaoyang Zeng. 196-199 [doi]
- A method of quadratic programming for mapping on NoC architectureJiayi Sheng, Liulin Zhong, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng. 200-203 [doi]
- A channel estimator for LTE downlink mapped on a multi-core processor platformMaofei He, Jiajie Zhang, Wenhua Fan, Zhiyi Yu, Xiaoyang Zeng. 204-207 [doi]
- Wideband spectrum sensing using the all-phase FFTLian Huai, Gerald E. Sobelman, Xiaofang Zhou. 208-211 [doi]
- A robust frame synchronization scheme for Broadband Power-line CommunicationChen Chen, Yuebin Huang, Yizhi Wang, Yun Chen, Xiaoyang Zeng. 212-215 [doi]
- FFT implementation with Multi-operand floating point unitsZhang Zhang, Dongge Wang, Yuteng Pan, Dan Wang, Xiaofang Zhou, Gerald E. Sobelman. 216-219 [doi]
- General lattice wave digital filter with phase compensation schemeYan Zhao, Jinyuan Zhou, Xiaofang Zhou, Gerald E. Sobelman. 220-223 [doi]
- A high efficient baseband transceiver for IEEE 802.15.4 LR-WPAN systemsShouyi Yin, Jianwei Cui, Ao Luo, Leibo Liu, Shaojun Wei. 224-227 [doi]
- System modeling and analysis of the IEEE 802.15.4 physical layer designJikang Xia, Lan Chen, Ying Li, Yinhao Zhou. 228-231 [doi]
- Towards the next generation of low-power test technologiesXiaoqing Wen. 232-235 [doi]
- Word error control algorithm through multi-reading for NAND Flash memoriesChong Zhang, Tsutomu Yoshihara. 236-239 [doi]
- A new scheme for testability improvement of ECC incorporated memoryLei Wang, Jianhua Jiang, Yumei Zhou, Gaofeng Ren. 240-243 [doi]
- A BIST scheme for high-speed Gain Cell eDRAMBing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin. 244-247 [doi]
- Variation-resilient voltage generation for SRAM weak cell testingChingwei Yeh, Yan-Nan Liu, Jinn-Shyan Wang, Pei-Yao Chang. 248-251 [doi]
- Single event upset immune latch circuit design using C-elementRamin Rajaei, Mahmoud Tabandeh, Bizhan Rashidian. 252-255 [doi]
- Challenges of electrostatic discharge (ESD) protection in emerging silicon nanowire technologyJuin J. Liou, Chang Jiang, Cao Guang-Biao, Chang Gung, Feng Chia. 256-258 [doi]
- A software/hardware co-debug platform for multi-core systemsKuen-Jong Lee, Alan P. Su, Long-Feng Chen, Jia-Wei Jhou, Jiff Kuo, Mark Liu. 259-262 [doi]
- HV CMOS orientated variation-aware layout and robust solutionGu Cong, Chen Hong. 263-266 [doi]
- Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCsYueming Yang, Heng Quan, Zewen Shi, Xiaoyang Zeng, Zhiyi Yu. 267-270 [doi]
- Addressing fault tolerance in 4-PAM signaling by using block codes for on/off-chip communicationArash Abtahi Forooshani, Fakhrul Zaman Rokhani. 271-274 [doi]
- A novel multi-finger layout strategy for GGnMOS ESD protection devicePeng Zhang, Yuan Wang, Song Jia, Xing Zhang. 275-278 [doi]
- Current status and future prospect of Phase Change MemoryByeungchul Kim, Yoon-Jong Song, Sujin Ahn, Younseon Kang, Hoon Jeong, Dongho Ahn, Seokwoo Nam, Gitae Jeong, Chilhee Chung. 279-282 [doi]
- Memristor models and circuits for controlling Process-VDD-Temperature variationsKwan-Hee Jo, Chul-Moon Jung, Kyeong-Sik Min. 283-286 [doi]
- The design of low leakage SRAM cell with high SNMHao Yan, Donghui Wang, Chaohuan Hou. 287-290 [doi]
- Novel RRAM programming technology for instant-on and high-security FPGAsXiaoyong Xue, Wenxiang Jian, Yufeng Xie, Qing Dong, Rui Yuan, Yinyin Lin. 291-294 [doi]
- A study of dual-Vt configurations of an 8T SRAM cell in 45nmWenbin Liu, Jinhui Wang, Wuchen Wu, Xiaohong Peng, Ligang Hou. 295-298 [doi]
- Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM)Meng-Fan Chang, Pi-Feng Chiu, Wei-Cheng Wu, Ching-Hao Chuang, Shyh-Shyuan Sheu. 299-302 [doi]
- A 55nm ultra high density two-port register file compiler with improved write replica techniqueZhao-Yong Zhang, Li Jun Zhang, Yi-Ping Zhang, Rui Feng Huang, Shou-Dao Wu, Jian-Bin Zheng. 303-306 [doi]
- Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOSRuifeng Huang, Jianbin Zheng, Lijun Zhang 0005, Zhaoyong Zhang, Hao Wu, Yue Yu. 307-310 [doi]
- Design of a single-ended cell based 65nm 32×32b 4R2W register fileBaoyu Xiong, Xingxing Zhang, Jun Han, Zhiyi Yu, Xiaoyang Zeng. 311-314 [doi]
- A 90 nm 16 Mb embedded phase-change memory macro with write current smoothing and enhanced write bandwidthHongwei Hong, Zheng Li, Qin Li, Ruizhe Wang, Charlie Hwang. 315-318 [doi]
- Separate projection and extended Cauer method for circuit reductionGoro Suzuki. 319-323 [doi]
- VLSI interconnect delay analysis method for ramp input signalNobuyuki Mihara, Goro Suzuki. 324-328 [doi]
- RRA-based multi-objective optimization to mitigate the worst cases of placementYiqiang Sheng, Atsushi Takahashi 0001, Shuichi Ueno. 329-332 [doi]
- Numerical characterization of multi-dielectric green's function for floating random walk based capacitance extractionHao Zhuang, Wenjian Yu, Gang Hu, Zuochang Ye. 333-336 [doi]
- Power grid sizing via convex programmingPeng Du, Shih-Hung Weng, Xiang Hu, Chung-Kuan Cheng. 337-340 [doi]
- Polarity optimization of XNOR/OR circuit area and power based on weighted sum methodHuihong Zhang, Pengjun Wang. 341-344 [doi]
- Don't let the X-bugs bite: Conquer elusive X-propagation issues early! Get them before they get you!Lisa Piper, Jin Zhang. 345-348 [doi]
- Meshim: A high-level performance simulation platform for three-dimensional network-on-chipMenwang Xie, Duoli Zhang, Yao Li. 349-352 [doi]
- Through-Silicon-Via assignment for 3D ICsJianchang Ao, Sheqin Dong, Song Chen, Satoshi Goto. 353-356 [doi]
- Incremental layout optimization for NoC designs based on MILP formulationJia Liu, Yuchun Ma, Ning Xu, Yu Wang. 357-360 [doi]
- Standard cell design of a low-leakage flip-flop with gate-length biasingJianping Hu, Jun Wang. 361-364 [doi]
- Debugging methodology and timing analysis in CDC solutionAkitoshi Matsuda, Jin Zhang. 365-368 [doi]
- Circuit simulation using matrix exponential methodShih-Hung Weng, Quan Chen, Chung-Kuan Cheng. 369-372 [doi]
- A new event driven testbench synthesis engine for FPGA emulationHaocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Pin Li. 373-376 [doi]
- An improved packing tool based on a dual-output basic logic elementXianyang Jiang, Ying Liu, Shilei Sun, Gaofeng Wang. 377-380 [doi]
- A test approach of combining partial scan with functional testing for high performance processorsQuanquan Li, Yingke Gao, Tiejun Zhang, Chaohuan Hou. 381-384 [doi]
- Automatic layout generator for embedded FPGA coresChaofan Yu, Lingli Wang, Xuegong Zhou. 385-388 [doi]
- An optimized mapping algorithm based on Simulated Annealing for regular NoC architectureLiulin Zhong, Jiayi Sheng, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng, Dian Zhou. 389-392 [doi]
- FPGA interconnect timing library based on the statistical methodXiangzhi Meng, Liguang Chen, Hao Zhou, Jian Wang, Meng Yang, Jinmei Lai. 393-396 [doi]
- Robustness and performance analysis on high speed ASIC design with canonical statistical timing modelSuoming Pu, Bo Yu, Xuan Zou. 397-400 [doi]
- Optimization of mixed polarity Reed-Muller expressions based on Whole Annealing Genetic AlgorithmMeng Yang, Hongying Xu. 401-404 [doi]
- CPIPQ: A common platform for silicon IP qualificationMark P. C. Mok, Kenneth C. K. Lo, Yuzhong Jiao, Yiu Kei Li. 405-408 [doi]
- Comprehensive electro-thermal(ET) analysis with considering ET couplingHuang Kun, Guoxing Zhao, Yang Xu, Zuying Luo. 409-412 [doi]
- Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithmJiawen Wang, Li Li 0003, Hongbing Pan, Shuzhuan He, Rong Zhang. 413-416 [doi]
- Mobility overlap-removal based timing-constrained schedulingSong Chen, Yuan Yao, Takeshi Yoshimura. 417-420 [doi]
- An effecient level-shifter floorplanning method for Multi-voltage designXiaolin Zhang, Zhi Lin, Song Chen, Takeshi Yoshimura. 421-424 [doi]
- The manufacturing of Si base thin film solar cell modulesTingkai Li. 425-429 [doi]
- Challenges and strategies in advanced CMOS technology developmentXiaomeng Chen. 430-432 [doi]
- Research on electromechanical model of micro-accelerometer based on SOI technologyKeqiang Qian, Wen Luo, Qi Yu. 433-436 [doi]
- CMOS compatible MEMs process for post interconnect single chip integration applicationXiaoxu Kang, Qingyun Zuo, Jiaqing Li, Chao Yuan, Yuhang Zhao. 437-440 [doi]
- Cascadable current-mode multifunction filter configuration using minimum number of CCTAs and grounded capacitorsXifeng Zhou, Jinguang Jiang, Shanshan Li. 441-444 [doi]
- A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter designXiaoyu Wang, Haigang Yang, Tao Yin, Fei Liu 0011. 445-448 [doi]
- A sigma-delta modulator with a novel chopper correlated double sampled integratorLuo Wang, Huihui Ji, Quan Sun. 449-452 [doi]
- VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter applicationJing Li, Ran Li, Ting Yi, Zhiliang Hong, Bill Yang Liu. 453-456 [doi]
- A continuous time sigma-delta modulator using time-domain quantizer and feedback elementSiliang Hua, Hao Yan, Yan Liu, Donghui Wang, Chaohuan Hou. 457-460 [doi]
- An analysis on a pseudo-differential dynamic comparator with load capacitance calibrationDaehwa Paik, Masaya Miyahara, Akira Matsuzawa. 461-464 [doi]
- Modeling of a double-sampling switched-capacitor bandpass delta-sigma modulator for multi-standard applicationsHong Chang, Wenxian Lu, Xu Cheng, Yawei Guo, Xiaoyang Zeng. 465-468 [doi]
- A time-domain flash ADC immune to voltage controlled delay line non-linearityYoung-Hwa Kim, SeongHwan Cho. 469-471 [doi]
- A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with split capacitor arraySeong Jin Cho, Yohan Hong, Taegeun Yoo, Kwang-Hyun Baek. 472-475 [doi]
- A 1.8V 100MS/s 10-bit pipelined folding A/D converter with 9.49 ENOB at Nyquist frequencyXiaojuan Li, Yintang Yang, Zhangming Zhu. 476-479 [doi]
- A sample-and-hold circuit for 10-bit 100MS/s pipelined ADCHaitao Wang, Hui Hong, Lingling Sun, Zhiping Yu. 480-483 [doi]
- A low power 10-bit 100-MS/s SAR ADC in 65nm CMOSJun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng. 484-487 [doi]
- A dual 12bit 80MSPS 3.3V Current-Steering DAC for HINOCHongming Chen, Xiaoyuan Chen, Yuhua Cheng. 488-491 [doi]
- A 4-channel 8-bit 650-MSample/s DAC with interpolation filter for embedded applicationQianqian Ha, Fan Ye, Chixiao Chen, Xiaoshi Zhu, Mingshuo Wang, Yu-Jing Lin, Ning Li, Junyan Ren. 492-495 [doi]
- A new current switch driver with improved dynamic performance used for 500MS/s, 12-bit Nyquist current-steering DACGuojia Liu, Lenian He, Xiaobo Xue, Qifeng Shi. 496-499 [doi]
- A 14-bit 2-GS/s DAC with SFDR>70dB up to 1-GHz in 65-nm CMOSRan Li, Qi Zhao, Ting Yi, Zhiliang Hong. 500-503 [doi]
- A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmittersLi Li, Jun Ma, Yawei Guo, Xu Cheng, Xiaoyang Zeng. 504-507 [doi]
- Energy efficient ADC design with low voltage operationAkira Matsuzawa. 508-511 [doi]
- A low-power 4.224GS/s sampler in 0.13-µm CMOS for IR UWB receiverYi Zhao, Jun Jiang, Ke Shao, Yajie Qin, Zhiliang Hong. 512-515 [doi]
- CMOS low-power subthreshold reference voltage utilizing self-biased body effectZhang Hao, Yimeng Zhang, Mengshu Huang, Yoshihara Tsutomu. 516-519 [doi]
- A precision 2.5V bandgap voltage reference with excellent initial accuracy of 0.25% for high resolution ADCsXiaozong Huang, Jing Zhang, Luncai Liu, Wengang Huang, Yanlin Zhang, Lei Yu. 520-523 [doi]
- A high-performance bandgap reference with advanced curvature-compensationZe-kun Zhou, Xiang-zhu Xu, Yue Shi, Xin-ming, Bo Zhang. 524-527 [doi]
- Novel flash ion sensitive field effect transistor for chemical sensor applicationsChao Sung Lai, Tseng-Fu Lu, Jer-Chyi Wang. 528-530 [doi]
- A model for energy quantization of single-electron transistor below 10nmXiaobao Chen, Zuocheng Xing, Bingcai Sui. 531-534 [doi]
- An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low powerXin Jiang, Ran Zhang, Takahiro Watanabe. 535-538 [doi]
- Linear Dropout Regulator based power distribution design under worst loadingAmirali Shayan Arani, Xiang Hu, Chung-Kuan Cheng, Wenjian Yu, Christopher Pan. 539-542 [doi]
- A unipolar-CMOS with recessed source/drain loadJyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang. 543-546 [doi]
- An analytical model for SOI triple RESURF devicesHaimeng Huang, Yongwei Wang, Xingbi Chen. 547-550 [doi]
- A study of second saturation effect of OPTVLD NMOSWenfang Du, Xingbi Chen. 551-554 [doi]
- Quantum mechanical effects on the threshold voltage of the evenly doped surrounding-gate MOSFETsGuanghui Mei, Peicheng Li, Guangxi Hu, Ran Liu 0001, Tingao Tang. 555-557 [doi]
- Effect of structural parameters on the performance and variations of nanosizes PNIN tunneling field effect transistorS. Q. Cheng, C. J. Yao, D. M. Huang. 558-561 [doi]
- Exploring 3D power distribution network physicsXiang Hu, Peng Du, Chung-Kuan Cheng. 562-565 [doi]
- An efficient solver for statistical capacitance extraction considering random process variationsRubing Bai, Shan Zeng, Qingqing Zhang, Wenjian Yu. 566-569 [doi]
- Performance evaluation modeling for reconfigurable processorShuang Liang, Shouyi Yin, Chongyong Yin, Leibo Liu, Shaojun Wei. 570-573 [doi]
- A high performance clock precharge SEU hardened flip-flopRiadul Islam, Seyed Ebrahim Esmaeili, Thouhidul Islam. 574-577 [doi]
- Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counterFengna Mei, Pengjun Wang. 578-581 [doi]
- A study of frequency synthesizer for AT-DMB applicationsJun Cheng, Sung Hoon Bang, Nak Yoon Kim, Yong Moon. 582-585 [doi]
- A new figure of Merit of LC oscilators considering frequency tuning rangeTakahiro Sato, Kenichi Okada, Akira Matsuzawa. 586-589 [doi]
- Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOSWufeng Wang, Peichen Jiang, Tingting Mo, Jianjun Zhou. 590-593 [doi]
- Design of a low-power low-phase-noise multi-mode divider with 25%-duty-cycle outputs in 0.13µm CMOSSong Hu, Weinan Li, Yumei Huang, Zhiliang Hong. 594-597 [doi]
- A noise rejective VCO with build-in active LC filterZhuo Ma, Yang Guo, Lunguo Xie, Rongrong Liu, Hongjian Zuo. 598-601 [doi]
- A 0.8ps minimum-resolution sub-exponent TDC for ADPLL in 0.13µm CMOSXiaolu Liu, Na Yan, Xi Tan, Hao Min. 602-605 [doi]
- 0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variationsChia-Wen Chang, Shyh-Jye Jou, Yuan-Hua Chu. 606-609 [doi]
- Digitally-controlled cell-based oscillator with multi-phase differential outputsMing-Chiuan Su, Shyh-Jye Jou. 610-613 [doi]
- Low phase noise injection-locked doubler-based quadrature CMOS VCOChen Lian, Wei Li, Haipeng Fu, Ning Li, Junyan Ren. 614-617 [doi]
- A thermal model for the top layer of 3D integrated circuits considering through silicon viasFengjuan Wang, Zhangming Zhu, Yintang Yang, Ning Wang. 618-620 [doi]
- Novel high uniformity readout circuit allowing microbolometers to operate with low noiseJian Lv, Yun Zhou, Baobin Liao, Yadong Jiang. 621-624 [doi]
- Integration of information security chips based on System-in-PackageTong Ran, Guoqiang Bai. 625-628 [doi]
- A new asynchronous delay-insensitive link based on a 1-of-4 LETS codeCan Wang, Qin Wang, Jian-Fei Jiang. 629-632 [doi]
- A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipelineYanfei Yang, Yintang Yang, Zhangming Zhu, Duan Zhou. 633-636 [doi]
- An ultra low power ASK demodulator for passive UHF RFID tagHongqiang Zong, Jinpeng Shen, Shan Liu, Mei Jiang, Qingyuan Ban, Ling Tang, Fanyu Meng, Xin'an Wang. 637-640 [doi]
- Improvement and parallel implementation of canny edge detection algorithm based on GPUShengxiao Niu, Jingjing Yang, Sheng Wang, Gengsheng Chen. 641-644 [doi]
- A new full current mode sense amplifier with compensation circuitYiqi Wang, Fazhao Zhao, Mengxin Liu, Zhengsheng Han. 645-648 [doi]
- An efficient 90nm technology-node GHz transceiver of on-chip global interconnectZaixiao Zheng, Zhigang Mao, Jian-Fei Jiang. 649-652 [doi]
- Electrochemical biosensor based on modified graphene oxide for tuberculosis diagnosisPei Zhang, Xiaosen Chai, Chun Xu, Jia Zhou. 653-656 [doi]
- Digital quadrature IF modulator using single-bit DACsRuimin Huang, Chaodong Ling, Jiaxian Wang. 657-660 [doi]
- Zero-crossing distortion analysis in one cycle controlled boost PFC for Low THDYani Li, Yintang Yang, Zhangming Zhu, Wei Qiang. 661-664 [doi]
- A simulation study of vertical tunnel field effect transistorsZhong-Fang Han, Guo-Ping Ru, Gang Ruan. 665-668 [doi]
- Determination of the trap states distribution in Poly-Si films using the OEMS modulationXiyue Li, Wanling Deng, Junkai Huang. 669-672 [doi]
- High efficiency and low power multi-rate LDPC decoder design for CMMBXiaobo Jiang, Hongyuan Li. 673-678 [doi]
- Area efficient LDPC decoder design for parallel layered decodingYuan Yao, Fan Ye, Junyan Ren. 679-682 [doi]
- Accelerating the data shuffle operations for FFT algorithms on SIMD DSPsKai Zhang, Shuming Chen, Sheng Liu, Yaohua Wang, Junhui Huang. 683-686 [doi]
- Automatic compilation flow for a coarse-grained reconfigurable processorHao Wang, Weiguang Sheng, Weifeng He. 687-690 [doi]
- Origin of high on-state current for dopant-segregated schottky MOSFETYang Tang, Liu-Lin Zhong, Yu-Long Jiang. 691-693 [doi]
- System level performance evaluation of three-dimensional integrated circuitLibo Qian, Zhangming Zhu, Yintang Yang. 694-697 [doi]
- An energy efficiency task scheduling algorithm for streaming applications on multiprocessor SoCShan Cao, Zhaolin Li, Shaojun Wei. 698-702 [doi]
- Analysis and architecture design of aggregation in BM3DWenjiang Liu, Yue Zhu, Tao Liu, Mengtian Rong, Hao Zhang. 703-706 [doi]
- A JTAG-based configuration circuit applied in SerDes chipXun Jiang, Xiaoxin Cui, Dunshan Yu. 707-710 [doi]
- An automated design flow for image processing filter in embedded systemsAkitoshi Matsuda, Shinichi Baba. 711-714 [doi]
- A novel channel estimation algorithm in OFDM power line communication systemHuidong Zhao, Yong Hei, Shushan Qiao. 715-718 [doi]
- Low power design for SoC with power management unitDaying Sun, Shen Xu, Weifeng Sun, Shengli Lu, Longxing Shi. 719-722 [doi]
- Improvement on branch scheduling for VLIW architectureLidan Bao, Hongmei Wang, Tiejun Zhang, Donghui Wang, Chaohuan Hou. 723-726 [doi]
- 4 field of symmetric cryptographyJianbo Xu, Zibin Dai, Yang Xuan, Yang Su. 727-730 [doi]
- A low-voltage differential injection locked divider with forward body biasHaipeng Fu, Hanchao Zhou, Yangyang Niu, Junyan Ren, Wei Li, Ning Li. 731-734 [doi]
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