Nikil D. Dutt - researchr alias

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2011

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable ArchitecturesGanghee Lee, Kiyoung Choi, Nikil D. Dutt. tcad, 30(5):637-650, 2011. [doi]

A Multi-Granularity Power Modeling Methodology for Embedded ProcessorsYoung-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt. tvlsi, 19(4):668-681, 2011. [doi]

2010

PoliMakE: a policy making engine for secure embedded software execution on chip-multiprocessorsLuis Angel D. Bathen, Nikil D. Dutt. cases 2010: 2 [doi]

Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable ArchitectureGanghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt. arc 2010: 231-243 [doi]

Towards reverse engineering the brain: Modeling abstractions and simulation frameworksJayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt, Jeffrey L. Krichmar. vlsi 2010: 1-6 [doi]

Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor ApplicationsSudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt. tvlsi, 18(9):1376-1380, 2010. [doi]

CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture SynthesisSudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt. tvlsi, 18(2):209-221, 2010. [doi]

2009

Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural ConsiderationsSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. tvlsi, 17(2):234-247, 2009. [doi]

A Methodology for Power-aware Pipelining via High-Level Performance Model EvaluationsLuis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha. mtv 2009: 19-24 [doi]

Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applicationsLuis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha. estimedia 2009: 45-54 [doi]

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia ApplicationsDoosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek. tcad, 28(4):554-567, 2009. [doi]

Fast Configurable-Cache Tuning With a Unified Second-Level CacheAnn Gordon-Ross, Frank Vahid, Nikil D. Dutt. tvlsi, 17(1):80-91, 2009. [doi]

Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia ApplicationsKyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian. tvlsi, 17(9):1343-1347, 2009. [doi]

Computing Spike-based Convolutions on GPUsJayram Moorkanikara Nageswaran, Nikil D. Dutt, Yingxue Wang, Tobi Delbrück. iscas 2009: 1917-1920 [doi]

Live Demonstration: Computing Spike-based Convolutions on GPUsJayram Moorkanikara Nageswaran, Nikil D. Dutt, Yingxue Wang, Tobi Delbrück. iscas 2009: 1921 [doi]

A configurable simulation environment for the efficient simulation of large-scale spiking neural networks on graphics processorsJayram Moorkanikara Nageswaran, Nikil D. Dutt, Jeffrey L. Krichmar, Alex Nicolau, Alexander V. Veidenbaum. NN, 22(5-6):791-800, 2009. [doi]

System-level PVT variation-aware power exploration of on-chip communication architecturesSudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi. todaes, 14(2), 2009. [doi]

Hybrid-compiled simulation: An efficient technique for instruction-set architecture simulationMehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt. tecs, 8(3), 2009. [doi]

2008

A framework for memory-aware multimedia application mapping on chip-multiprocessorsLuis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha. estimedia 2008: 89-94 [doi]

EditorialNikil D. Dutt. todaes, 13(3), 2008. [doi]

Thermal Aware Global Routing of VLSI Chips for Enhanced ReliabilityAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. isqed 2008: 470-475 [doi]

Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming ApplicationsIlya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt. tcad, 27(8):1439-1452, 2008. [doi]

PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT ProcessorsDeepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi. vlsid 2008: 421-427 [doi]

Register File Power Reduction Using Bypass Sensitive CompilerSanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie. tcad, 27(6):1155-1159, 2008. [doi]

2007

Introduction of Architecturally Visible Storage in Instruction Set ExtensionsPartha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne. tcad, 26(3):435-446, 2007. [doi]

Quality-Based Backlight Optimization for Video Playback on Handheld DevicesLiang Cheng, Shivajit Mohapatra, Magda El Zarki, Nikil D. Dutt, Nalini Venkatasubramanian. amm, 2007, 2007. [doi]

STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCsAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. vlsid 2007: 559-564 [doi]

LEAF: A System Level Leakage-Aware Floorplanner for SoCsAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. aspdac 2007: 274-279 [doi]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich, editors, ACM, 2007.

A Probabilistic Formal Analysis Approach to Cross Layer Optimization in Distributed Embedded SystemsMinyoung Kim, Mark-Oliver Stehr, Carolyn L. Talcott, Nikil D. Dutt, Nalini Venkatasubramanian. fmoods 2007: 285-300 [doi]

Instruction set synthesis with efficient instruction encoding for configurable processorsJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. todaes, 12(1), 2007. [doi]

A Framework for Cosynthesis of Memory and Communication Architectures for MPSoCSudeep Pasricha, Nikil D. Dutt. tcad, 26(3):408-420, 2007. [doi]

BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoCSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. tcad, 26(8):1454-1464, 2007. [doi]

Automatic Design Space Exploration of Register Bypasses in Embedded ProcessorsAviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek. tcad, 26(12):2102-2115, 2007. [doi]

2006

Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic ReconfigurationSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. tvlsi, 14(11):1189-1202, 2006. [doi]

Performance and Energy Benefits of Instruction Set Extensions in an FPGA Soft CorePartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Paolo Ienne, Laura Pozzi. vlsid 2006: 651-656 [doi]

Automatic identification of application-specific functional units with architecturally visible storagePartha Biswas, Nikil D. Dutt, Paolo Ienne, Laura Pozzi. date 2006: 212-217 [doi]

ISEGEN: an iterative improvement-based ISE generation technique for fast customization of processorsPartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne. tvlsi, 14(7):754-762, 2006. [doi]

Software annotations for power optimization on mobile devicesRadu Cornea, Alexandru Nicolau, Nikil D. Dutt. date 2006: 684-689 [doi]

EditorialNikil D. Dutt. todaes, 11(1):1-2, 2006. [doi]

Floorplan driven leakage power aware IP-based SoC design space explorationAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. codes 2006: 118-123 [doi]

Energy efficient watermarking on mobile devices using proxy-based partitioningArun Kejariwal, Sumit Gupta, Alexandru Nicolau, Nikil D. Dutt, Rajesh K. Gupta. tvlsi, 14(6):625-636, 2006. [doi]

Bypass aware instruction scheduling for register file power reductionSanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie. lctrts 2006: 173-181 [doi]

System-level power-performance trade-offs in bus matrix communication architecture synthesisSudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt. codes 2006: 300-305 [doi]

COSMECA: application specific co-synthesis of memory and communication architectures for MPSoCSudeep Pasricha, Nikil D. Dutt. date 2006: 700-705 [doi]

FABSYN: floorplan-aware bus architecture synthesisSudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane. tvlsi, 14(3):241-253, 2006. [doi]

Constraint-driven bus matrix synthesis for MPSoCSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. aspdac 2006: 30-35 [doi]

Generic Processor Modeling for Automatically Generating Very Fast Cycle-Accurate SimulatorsMehrdad Reshadi, Bita Gorjiara, Nikil D. Dutt. tcad, 25(12):2904-2918, 2006. [doi]

Compilation framework for code size reduction using reduced bit-width ISAs (rISAs)Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau. todaes, 11(1):123-146, 2006. [doi]

Retargetable pipeline hazard detection for partially bypassed processorsAviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau. tvlsi, 14(8):791-801, 2006. [doi]

2005

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfigurationSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. dac 2005: 335-340 [doi]

Considering Run-Time Reconfiguration Overhead in Task Graph Transformations for Dynamically Reconfigurable ArchitecturesSudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt. fccm 2005: 273-274 [doi]

ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative ImprovementPartha Biswas, Sudarshan Banerjee, Nikil D. Dutt, Laura Pozzi, Paolo Ienne. date 2005: 1246-1251 [doi]

Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set ExtensionsPartha Biswas, Nikil D. Dutt. TC, 54(10):1216-1226, 2005. [doi]

Quality Adapted Backlight Scaling (QABS) for Video Streaming to Mobile Handheld DevicesLiang Cheng, Stefano Bossi, Shivajit Mohapatra, Magda El Zarki, Nalini Venkatasubramanian, Nikil D. Dutt. icn 2005: 662-671 [doi]

EditorialNikil D. Dutt. todaes, 10(1):1-2, 2005. [doi]

Fast configurable-cache tuning with a unified second-level cacheAnn Gordon-Ross, Frank Vahid, Nikil D. Dutt. islped 2005: 323-326 [doi]

FORAY-GEN: Automatic Generation of Affine Functions for Memory OptimizationsIlya Issenin, Nikil D. Dutt. date 2005: 808-813 [doi]

An Introduction to the Plasma LanguageBrian Kahne, Aseem Gupta, Peter Wilson, Nikil D. Dutt. mtv 2005: 12-22 [doi]

Probability Based Power Aware Error Resilient CodingMinyoung Kim, Hyunok Oh, Nikil D. Dutt, Alexandru Nicolau, Nalini Venkatasubramanian. icdcsw 2005: 307-313 [doi]

A methodology for validation of microprocessors using symbolic simulationPrabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir. ijes, 1(1/2):14-22, 2005. [doi]

Functional Coverage Driven Test Generation for Validation of Pipelined ProcessorsPrabhat Mishra, Nikil D. Dutt. date 2005: 678-683 [doi]

Functional verification of programmable embedded architectures - a top-down approachPrabhat Mishra, Nikil D. Dutt. Springer, 2005.

A Cross-Layer Approach for Power-Performance Optimization in Distributed Mobile SystemsShivajit Mohapatra, Radu Cornea, Hyunok Oh, Kyoungwoo Lee, Minyoung Kim, Nikil D. Dutt, Rajesh Gupta, Alexandru Nicolau, Sandeep K. Shukla, Nalini Venkatasubramanian. ipps 2005: [doi]

Shift buffering technique for automatic code synthesis from synchronous dataflow graphsHyunok Oh, Nikil D. Dutt, Soonhoi Ha. codes 2005: 51-56 [doi]

Single appearance schedule with dynamic loop count for minimum data buffer from synchronous dataflow graphsHyunok Oh, Nikil D. Dutt, Soonhoi Ha. cases 2005: 157-165 [doi]

Floorplan-aware automated synthesis of bus-based communication architecturesSudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane. dac 2005: 565-570 [doi]

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator GenerationMehrdad Reshadi, Nikil D. Dutt. date 2005: 786-791 [doi]

A generalized technique for energy-efficient operating voltage set-up in dynamic voltage scaled processorsJaewon Seo, Nikil D. Dutt. aspdac 2005: 836-841 [doi]

Optimal integration of inter-task and intra-task dynamic voltage scaling techniques for hard real-time applicationsJaewon Seo, Taewhan Kim, Nikil D. Dutt. iccad 2005: 450-455

Aggregating processor free time for energy reductionAviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau. codes 2005: 154-159 [doi]

PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded ProcessorsAviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie. date 2005: 1264-1269 [doi]

2004

Energy-Aware System Design for Wireless MultimediaHans Van Antwerpen, Nikil D. Dutt, Rajesh K. Gupta, Shivajit Mohapatra, Cristiano Pereira, Nalini Venkatasubramanian, Ralph von Vignau. date 2004: 1124-1131 [doi]

FIFO power optimization for on-chip networksSudarshan Banerjee, Nikil D. Dutt. glvlsi 2004: 187-191 [doi]

Efficient search space exploration for HW-SW partitioningSudarshan Banerjee, Nikil D. Dutt. codes 2004: 122-127 [doi]

Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable ArchitecturesNikhil Bansal, Sumit Gupta, Nikil D. Dutt, Alexandru Nicolau, Rajesh K. Gupta. fpl 2004: 891-899 [doi]

Using global code motions to improve the quality of results for high-level synthesisSumit Gupta, Nicolae Savoiu, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. tcad, 23(2):302-312, 2004. [doi]

Coordinated parallelizing compiler optimizations and high-level synthesisSumit Gupta, Rajesh K. Gupta, Nikil D. Dutt, Alexandru Nicolau. todaes, 9(4):441-470, 2004. [doi]

Analytical models for leakage power estimation of memory array structuresMahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir. codes 2004: 146-151 [doi]

IDAP: a tool for high-level power estimation of custom array structuresMahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir. tcad, 23(9):1361-1369, 2004. [doi]

Functional Verification of Pipelined Processors: A Case StudyPrabhat Mishra, Nikil D. Dutt, Yaron Kashai. mtv 2004: 79-84 [doi]

Functional Validation of Programmable ArchitecturesPrabhat Mishra, Nikil D. Dutt. dsdm 2004: 12-19 [doi]

Dynamic Backlight Adaptation for Low-Power Handheld DevicesSudeep Pasricha, Manev Luthra, Shivajit Mohapatra, Nikil D. Dutt, Nalini Venkatasubramanian. dt, 21(5):398-405, 2004. [doi]

Fast exploration of bus-based on-chip communication architecturesSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. codes 2004: 242-247 [doi]

Extending the transaction level modeling approach for fast communication architecture explorationSudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane. dac 2004: 113-118 [doi]

Operation tables for scheduling in the presence of incomplete bypassingAviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau. codes 2004: 194-199 [doi]

Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA)Aviral Shrivastava, Nikil D. Dutt. aspdac 2004: 475-477 [doi]

2003

Exploring Efficient Operating Points for Voltage Scaled Embedded Processor CoresMarcio Buss, Tony Givargis, Nikil D. Dutt. rtss 2003: 275 [doi]

Configurable Processors for Embedded ComputingNikil D. Dutt, Kiyoung Choi. Computer, 36(1):120-123, 2003. [doi]

Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive DesignsSumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. date 2003: 10270-10275 [doi]

SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler TransformationsSumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. vlsid 2003: 461-466 [doi]

Energy-efficient instruction set synthesis for application-specific processorsJong-eun Lee, Kiyoung Choi, Nikil D. Dutt. islped 2003: 330-333 [doi]

Interface Synthesis using Memory Mapping for an FPGA PlatformManev Luthra, Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau. iccd 2003: 140-145 [doi]

IDAP: A Tool for High Level Power Estimation of Custom Array StructuresMahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir. iccad 2003: 113-119 [doi]

Adaptive low-power address encoding techniques using self-organizing listsMahesh Mamidipaka, Daniel S. Hirschberg, Nikil D. Dutt. tvlsi, 11(5):827-834, 2003. [doi]

A Methodology for Validation of Microprocessors using Equivalence CheckingPrabhat Mishra, Nikil D. Dutt. mtv 2003: 83-88 [doi]

Integrated power management for video streaming to mobile handheld devicesShivajit Mohapatra, Radu Cornea, Nikil D. Dutt, Alexandru Nicolau, Nalini Venkatasubramanian. mm 2003: 582-591 [doi]

Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld DevicesSudeep Pasricha, Shivajit Mohapatra, Manev Luthra, Nikil D. Dutt, Nalini Venkatasubramanian. estimedia 2003: 11-17

An efficient retargetable framework for instruction-set simulationMehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil D. Dutt. codes 2003: 13-18 [doi]

Instruction set compiled simulation: a technique for fast and flexible instruction set simulationMehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt. dac 2003: 758-763 [doi]

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