Abstract is missing.
- X Marks the Spot: Scan-Flip-Flop Clustering for Faster-than-at-Speed TestMatthias Kampmann, Sybille Hellebrand. 1-6 [doi]
- Crypt-Delay: Encrypting IP Cores with Capabilities for Gate-level Logic and Delay SimulationsParameswaran Ramanathan, Kewal K. Saluja. 7-12 [doi]
- On the Switching Activity in Faulty Circuits During Test ApplicationIrith Pomeranz, Sudhakar M. Reddy. 13-18 [doi]
- Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan TestStefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte. 19-24 [doi]
- Repairable Cell-Based Chip Design for Simultaneous Yield Enhancement and Fault DiagnosisSheng-Lin Lin, Cheng-Hung Wu, Kuen-Jong Lee. 25-30 [doi]
- A New Approach for Debugging Logic Circuits without Explicitly Debugging Their FunctionalityAmir Masoud Gharehbaghi, Masahiro Fujita. 31-36 [doi]
- A Verification Guided Approach for Selective Program Transformations for Approximate ComputingSayandeep Mitra, Moumita Das, Ansuman Banerjee, Kausik Datta, Tsung-Yi Ho. 37-42 [doi]
- Property Coverage Analysis Based Trustworthiness Verification for Potential Threats from EDA ToolsYingxin Qiu, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li 0001. 43-48 [doi]
- Efficient Attack on Non-linear Current Mirror PUF with Genetic AlgorithmQingli Guo, Jing Ye, Yue Gong, Yu Hu, Xiaowei Li 0001. 49-54 [doi]
- Noise-Resilient SRAM Physically Unclonable Function Design for SecuritySujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee. 55-60 [doi]
- On Test Points Enhancing Hardware SecurityElham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Justyna Zawada. 61-66 [doi]
- Side-Channel Attack on Flipped Scan ChainsSying-Jyan Wang, Ting-Jui Choi, Katherine Shu-Min Li. 67-72 [doi]
- Test and Reliability Issues in 2.5D and 3D IntegrationMehdi Baradaran Tahoori, Krishnendu Chakrabarty. 73 [doi]
- Testing of Interposer-Based 2.5D Integrated Circuits: Challenges and SolutionsRan Wang, Krishnendu Chakrabarty. 74-79 [doi]
- Pre-Bond and Post-Bond Testing of TSVs and Die-to-Die InterconnectsShi-Yu Huang. 80-85 [doi]
- Multicast Test Architecture and Test Scheduling for Interposer-Based 2.5D ICsShengcheng Wang, Ran Wang, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 86-91 [doi]
- A Study on the Transfer Function Based Analog Fault Model for Linear and Time-Invariant Continuous-Time Analog CircuitsHao-Chiao Hong, Long-Yi Lin. 92-95 [doi]
- Concurrent Stimulus and Defect Magnitude Optimization for Detection of Weakest Shorts and Opens in Analog CircuitsBarry John Muldrey, Sabyasachi Deyati, Abhijit Chatterjee. 96-101 [doi]
- Model-Free Testing of Analog CircuitsMehrdad Heydarzadeh, Hao Luo, Mehrdad Nourani. 102-106 [doi]
- Scan Chain Adaptation through ECOJasvir Singh, Anuj Grover, Mausumi Pohit, Anurag Singh Baghel, Gurjit Kaur, Shalini Pathak. 107-112 [doi]
- Test Strategies for Reconfigurable Scan NetworksMichael A. Kochte, Rafal Baranowski, Marcel Schaal, Hans-Joachim Wunderlich. 113-118 [doi]
- Test Time Minimization in Reconfigurable Scan NetworksRiccardo Cantoro, Marco Palena, Paolo Pasini, Matteo Sonza Reorda. 119-124 [doi]
- Rectangular Waveform Generation with Harmonics SuppressionMasayuki Kawabata, Koji Asami, Shohei Shibuya, Tomonori Yanagida, Haruo Kobayashi. 125 [doi]
- Achieving Acceptable Bit Error Rate for 40 Gbps Link Using Signal Conditioning TechniquesJayalaxmi Satishkumar, Nagesh Vaidya. 126 [doi]
- Design and Implementation of EMIB Testing on 2.5D FPGA TransceiverLai Pheng Tan, Shen Shen Lee, Kian Hui Wong. 127 [doi]
- Application of Data Mining Based Scan Diagnosis Yield Analysis in a Foundry and Fabless Working EnvironmentHao Shen, Lance Shen, Pierce Xu, Wu Yang, Junna Zhong. 128 [doi]
- rosTest: Universal Test Framework for Real-Time Operating SystemSiaw Chen Lee, Soon Ee Ong. 129 [doi]
- An Optical/Electrical Test System for 100-Gb/s Optical Interconnection Devices for High Volume ProductionTakeshi Mizushima, Kazuki Shirahata, Tasuku Fujibe, Hidenobu Matsumura, Daisuke Watanabe, Hiroyuki Mineo, Shin Masuda. 130 [doi]
- Multi-configuration Scan Structure for Various PurposesHiroyuki Iwata, Jun Matsushima. 131 [doi]
- On Achieving Maximal Chain Diagnosis Resolution through Test Pattern SelectionXijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng. 132-137 [doi]
- A Joint Diagnostic Test Generation Procedure with Dynamic Test CompactionM. Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman. 138-143 [doi]
- A Neural-Network-Based Fault ClassifierLaura Rodríguez Gómez, Hans-Joachim Wunderlich. 144-149 [doi]
- High-Throughput Transistor-Level Fault Simulation on GPUsEric Schneider, Hans-Joachim Wunderlich. 150-155 [doi]
- Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware TestHsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu. 156-160 [doi]
- Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D Network-on-Chip SystemsKhanh N. Dang, Michael Conrad Meyer, Yuichi Okuyama, Abderazek Ben Abdallah. 161-166 [doi]
- An IR-Drop Aware Test Pattern Generator for Scan-Based At-Speed TestingPo-Fan Hou, Yi-Tsung Lin, Jiun-Lang Huang, Ann Shih, Zoe F. Conroy. 167-172 [doi]
- Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan TestStephan Eggersglüß, Stefan Holst, Daniel Tille, Kohei Miyase, Xiaoqing Wen. 173-178 [doi]
- On Optimal Power-Aware Path SensitizationMatthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian. 179-184 [doi]
- Automated Optimization of Scan Chain Structure for Test Compression-Based DesignsHarshad Dhotre, Mehdi Dehbashi, Ulrike Pfannkuchen, Klaus Hofmann. 185-190 [doi]
- Critical-Area-Aware Test Pattern Generation and ReorderingShingo Inuyama, Masayuki Arai, Kazuhiko Iwasaki. 191-196 [doi]
- Efficient Cell-Aware Fault Modeling by Switch-Level Test GenerationHarry H. Chen, Simon Y.-H. Chen, Po-Yao Chuang, Cheng-Wen Wu. 197-202 [doi]
- A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BISTTakaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen. 203-208 [doi]
- Structure-Based Methods for Selecting Fault-Detection-Strengthened FF under Multi-cycle Test with Sequential ObservationSenling Wang, Hanan T. Al-Awadhi, Soh Hamada, Yoshinobu Higami, Hiroshi Takahashi, Hiroyuki Iwata, Jun Matsushima. 209-214 [doi]
- Autonomous Testing for 3D-ICs with IEEE Std. 1687Jin-Cun Ye, Michael A. Kochte, Kuen-Jong Lee, Hans-Joachim Wunderlich. 215-220 [doi]
- Die-to-Die Clock Skew Characterization and Tuning for 2.5D ICsShi-Yu Huang, Chih-Chieh Zheng. 221-226 [doi]
- Managing Reliability of Integrated Circuits: Lifetime Metering and Design for HealingSandip Kundu. 227 [doi]
- Highly Dependable Multi-processor SoCs Employing Lifetime Prediction Based on Health MonitorsYong Zhao, Hans G. Kerkhoff. 228-233 [doi]
- Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node ControlSong Bian, Michihiro Shintani, Zheng Wang 0020, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato. 234-239 [doi]
- Modeling Residual Lifetime of an IC Considering Spatial and Inter-Temporal Temperature VariationsMd. Nazmul Islam, Sandip Kundu. 240-245 [doi]
- Functional Diagnosis for Graceful Degradation of NoC SwitchesAtefe Dalirsani, Hans-Joachim Wunderlich. 246-251 [doi]
- Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS TechnologyAibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang. 252-256 [doi]
- Quality Aware Error Detection in 2-D Separable Linear TransformationShih-Hsin Hu, Jacob A. Abraham. 257-262 [doi]
- An Optical Interconnection Test Method Applicable to 100-Gb/s Transceivers Using an ATE Based HardwareKazuki Shirahata, Takeshi Mizushima, Tasuku Fujibe, Hidenobu Matsumura, Tomoyuki Itakura, Masahiro Ishida, Daisuke Watanabe, Shin Masuda. 263-268 [doi]
- An Ultra-High-Speed Test Module and FPGA-Based Development PlatformTe-Hui Chen, David C. Keezer. 269-274 [doi]
- Parametric Fault Detection in Analog Circuits: A Statistical ApproachSupriyo Srimani, Kasturi Ghosh, Hafizur Rahaman. 275-280 [doi]
- A Test Method for Finding Boundary Currents of 1T1R Memristor MemoriesTzu-Ying Lin, Yong-Xiao Chen, Jin-Fu Li, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou. 281-286 [doi]
- Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash MemoriesShyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume. 287-292 [doi]
- Evaluation Technique for Soft-Error Rate in Terrestrial Environment Utilizing Low-Energy Neutron IrradiationTakumi Uezono, Tadanobu Toba, Ken-ichi Shimbo, Fumihiko Nagasaki, Kenji Kawamura. 293-297 [doi]
- Aging-Leakage Tradeoffs Using Multi-Vth Cell LibraryHao Luo, Mehrdad Heydarzadeh, Mehrdad Nourani. 298-303 [doi]
- Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler ProgramsFrancesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar. 304-309 [doi]
- Combined Impact of BTI and Temperature Effect Inversion on Circuit PerformanceWarin Sootkaneung, Sasithorn Chookaew, Suppachai Howimanporn. 310-315 [doi]