Abstract is missing.
- The mobile society - chances and challenges for micro- and power electronicsKlaus Meder. 1 [doi]
- New foundry models - accelerations in transformations of the semiconductor industryMojy Chian. 2 [doi]
- Automated generation of directed tests for transition coverage in cache coherence protocolsXiaoke Qin, Prabhat Mishra. 3-8 [doi]
- On ESL verification of memory consistency for system-on-chip multiprocessingEberle A. Rambo, Olav P. Henschel, Luiz C. V. dos Santos. 9-14 [doi]
- Generating instruction streams using abstract CSPYoav Katz, Michal Rimon, Avi Ziv. 15-20 [doi]
- A cycle-approximate, mixed-ISA simulator for the KAHRISMA architectureTimo Stripf, Ralf König, Jürgen Becker. 21-26 [doi]
- A clustering-based scheme for concurrent trace in debugging NoC-based multicore systemsJianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang 0008, Xiaowei Li 0001. 27-32 [doi]
- CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memoryKe Chen, Sheng Li, Naveen Muralimanohar, Jung Ho Ahn, Jay B. Brockman, Norman P. Jouppi. 33-38 [doi]
- TagTM - accelerating STMs with hardware tags for fast meta-data accessSrdjan Stipic, Sasa Tomic, Ferad Zyulkyarov, Adrián Cristal, Osman S. Ünsal, Mateo Valero. 39-44 [doi]
- Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache designYu-Ting Chen, Jason Cong, Hui Huang 0001, Bin Liu 0006, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman. 45-50 [doi]
- DRAM selection and configuration for real-time mobile systemsManil Dev Gomony, Christian Weis, Benny Akesson, Norbert Wehn, Kees Goossens. 51-56 [doi]
- Using timing analysis for the design of future switched based Ethernet automotive networksJonas Rox, Rolf Ernst, Paolo Giusto. 57-62 [doi]
- Fair energy resource allocation by minority game algorithm for smart buildingsChun Zhang, Wei Wu, Hantao Huang, Hao Yu. 63-68 [doi]
- On demand dependent deactivation of automotive ECUsChristoph Schmutzler, Martin Simons, Jürgen Becker. 69-74 [doi]
- Smart power unit with ultra low power radio trigger capabilities for wireless sensor networksMichele Magno, Stevan Jovica Marinkovic, Davide Brunelli, Emanuel M. Popovici, Brendan O'Flynn, Luca Benini. 75-80 [doi]
- IR-drop analysis of graphene-based power distribution networksSandeep Miryala, Andrea Calimera, Enrico Macii, Massimo Poncino. 81-86 [doi]
- Off-path leakage power aware routing for SRAM-based FPGAsKeheng Huang, Yu Hu, Xiaowei Li 0001, Bo Liu, Hongjin Liu, Jian Gong. 87-92 [doi]
- Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimizationAdam Makosiej, Olivier Thomas, Andrei Vladimirescu, Amara Amara. 93-98 [doi]
- Post-synthesis leakage power minimizationMohammad Rahman, Carl Sechen. 99-104 [doi]
- Fast and lightweight support for nested parallelism on cluster-based embedded many-coresAndrea Marongiu, Paolo Burgio, Luca Benini. 105-110 [doi]
- A divide and conquer based distributed run-time mapping methodology for many-core platformsIraklis Anagnostopoulos, Alexandros Bartzas, Georgios Kathareios, Dimitrios Soudris. 111-116 [doi]
- Dual Greedy: Adaptive garbage collection for page-mapping solid-state disksWen-Huei Lin, Li-Pin Chang. 117-122 [doi]
- EDA solutions to new-defect detection in advanced process technologiesErik Jan Marinissen, Gilbert Vandling, Sandeep Kumar Goel, Friedrich Hapke, Jason Rivers, Nikolaus Mittermaier, Swapnil Bahl. 123-128 [doi]
- Beyond CMOS - benchmarking for future technologiesClivia M. Sotomayor Torres, Jouni Ahopelto, Mart W. M. Graef, R. M. Popp, Wolfgang Rosenstiel. 129-134 [doi]
- Accurately timed transaction level models for virtual prototyping at high abstraction levelKun Lu, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 135-140 [doi]
- Out-of-order parallel simulation for ESL designWeiwei Chen, Xu Han, Rainer Dömer. 141-146 [doi]
- A probabilistic analysis method for functional qualification under Mutation AnalysisHsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen. 147-152 [doi]
- Approximating checkers for simulation accelerationBiruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco. 153-158 [doi]
- Guidelines for model based systems engineeringDierk Steinbach. 159-160 [doi]
- SURF algorithm in FPGA: A novel architecture for high demanding industrial applicationsNiccolò Battezzati, Stefano Colazzo, M. Maffione, L. Senepa. 161-162 [doi]
- NOCEVE: Network on chip emulation and verification environmentOmar Hammami, Xinyu Li, Jean-Marc Brault. 163-164 [doi]
- Investigating the effects of Inverted Temperature Dependence (ITD) on clock distribution networksAlessandro Sassone, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino, Rich Goldman, Vazgen Melikyan, Eduard Babayan, Salvatore Rinaudo. 165-166 [doi]
- Challenges in verifying an integrated 3D designTsunwai Gary Yip, Chuan Yung Hung, Venu Iyengar. 167-168 [doi]
- Multiple-source and multiple-destination charge migration in hybrid electrical energy storage systemsYanzhi Wang, Qing Xie, Massoud Pedram, Younghyun Kim, Naehyuck Chang, Massimo Poncino. 169-174 [doi]
- Benefits of green energy and proportionality in high speed wide area networks connecting data centersBaris Aksanli, Tajana Simunic Rosing, Inder Monga. 175-180 [doi]
- Quantifying the impact of frequency scaling on the energy efficiency of the single-chip cloud computerAndrea Bartolini, MohammadSadegh Sadri, John-Nicholas Furst, Ayse Kivilcim Coskun, Luca Benini. 181-186 [doi]
- Neighbor-aware dynamic thermal management for multi-core platformGuanglei Liu, Ming Fan, Gang Quan. 187-192 [doi]
- Playing games with scenario- and resource-aware SDF graphs through policy iterationYang Yang, Marc Geilen, Twan Basten, Sander Stuijk, Henk Corporaal. 194-199 [doi]
- Verifying timing synchronization constraints in distributed embedded architecturesA. C. Rajeev, Swarup Mohalik, S. Ramesh. 200-205 [doi]
- Task implementation of synchronous finite state machinesMarco Di Natale, Haibo Zeng. 206-211 [doi]
- Enabling dynamic assertion-based verification of embedded software through model-driven designGiuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli. 212-217 [doi]
- NBTI mitigation by optimized NOP assignment and insertionFarshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori. 218-223 [doi]
- An accurate Single Event Effect digital design flow for reliable system level designJulian J. H. Pontes, Ney Calazans, Pascal Vivet. 224-229 [doi]
- Cross entropy minimization for efficient estimation of SRAM failure rateMohammed Abdul Shahid. 230-235 [doi]
- Experimentally driven verification of synthetic biological circuitsBoyan Yordanov, Evan Appleton, Rishi Ganguly, Ebru Aydin Gol, Swati Banerjee Carr, Swapnil Bhatia, Traci Haddock, Calin Belta, Douglas Densmore. 236-241 [doi]
- Genetic/bio design automation for (re-)engineering biological systemsSoha Hassoun. 242-247 [doi]
- Fast cycle estimation methodology for instruction-level emulatorDavid Thach, Yutaka Tamiya, Shinya Kuwamura, Atsushi Ike. 248-251 [doi]
- Verification coverage of embedded multicore applicationsEtem Deniz, Alper Sen 0001, Jim Holt. 252-255 [doi]
- Hazard driven test generation for SMT processorsPadmaraj Singh, Vijaykrishnan Narayanan, David L. Landis. 256-259 [doi]
- Extending the lifetime of NAND flash memory by salvaging bad blocksChundong Wang, Weng-Fai Wong. 260-263 [doi]
- A case study on the application of real phase-change RAM to main memory subsystemSuknam Kwon, Dongki Kim, Youngsik Kim, Sungjoo Yoo, Sunggu Lee. 264-267 [doi]
- A high-performance dense block matching solution for automotive 6D-visionHenning Sahlbach, Sean Whitty, Rolf Ernst. 268-271 [doi]
- Optimization intensive energy harvestingMahsan Rofouei, Mohammad Ali Ghodrat, Miodrag Potkonjak, Alfonso Martinez-Nova. 272-275 [doi]
- Designing FlexRay-based automotive architectures: A holistic OEM approachPaul Milbredt, Michael Glaß, Martin Lukasiewycz, Andreas Steininger, Jürgen Teich. 276-279 [doi]
- Virtualized on-chip distributed computing for heterogeneous reconfigurable multi-core systemsStephan Werner, Oliver Oey, Diana Göhringer, Michael Hübner, Jürgen Becker. 280-283 [doi]
- VaMV: Variability-aware Memory VirtualizationLuis Angel D. Bathen, Nikil D. Dutt, Alex Nicolau, Puneet Gupta. 284-287 [doi]
- Hybrid simulation for extensible processor coresJovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid. 288-291 [doi]
- Leveraging reconfigurability to raise productivity in FPGA functional debugZissis Poulos, Yu-Shen Yang, Jason Anderson, Andreas G. Veneris, Bao Le. 292-295 [doi]
- MOUSSE: Scaling modelling and verification to complex Heterogeneous Embedded Systems evolutionMarkus Becker, Gilles B. Defo, Franco Fummi, Wolfgang Müller 0003, Graziano Pravadelli, Sara Vinco. 296-299 [doi]
- Run-time power-gating in caches of GPUs for leakage energy savingsYue Wang, Soumyaroop Roy, Nagarajan Ranganathan. 300-303 [doi]
- Automatic generation of functional models for embedded processor extensionsFei Sun. 304-307 [doi]
- An integrated test generation tool for enhanced coverage of Simulink/Stateflow modelsPrakash Peranandam, Sachin Raviram, Manoranjan Satpathy, Anand Yeolekar, Ambar A. Gadkari, S. Ramesh. 308-311 [doi]
- Model driven resource usage simulation for critical embedded systemsMichael Lafaye, Laurent Pautet, Etienne Borde, Marc Gatti, David Faura. 312-315 [doi]
- RAG: An efficient reliability analysis of logic circuits on graphics processing unitsMin Li, Michael S. Hsiao. 316-319 [doi]
- CATRA- congestion aware trapezoid-based routing algorithm for on-chip networksMasoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 320-325 [doi]
- An MILP-based aging-aware routing algorithm for NoCsKshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy. 326-331 [doi]
- AFRA: A low cost high performance reliable routing for 3D mesh NoCsSara Akbari, Ali Shafiee, Mahmood Fathy, Reza Berangi. 332-337 [doi]
- Middleware services for network interoperability in smart energy efficient buildingsEdoardo Patti, Andrea Acquaviva, Francesco Abate, Anna Osello, A. Cocuccio, Marco Jahn, Marc Jentsch, Enrico Macii. 338-339 [doi]
- Low-power embedded system for real-time correction of fish-eye automotive camerasMauro Turturici, Sergio Saponara, Luca Fanucci, Emilio Franchi. 340-341 [doi]
- Mechatronic system for energy efficiency in bus transportMonica Donno, Aleck Ferrari, Annalisa Scarpelli, Pietro Perlo, Alberto Bocca. 342-343 [doi]
- Intelligent and collaborative embedded computing in automation engineeringMohammad Abdullah Al Faruque, Arquimedes Canedo. 344-345 [doi]
- Variation-aware leakage power model extraction for system-level hierarchical power analysisYang Xu, Bing Li, Ralph Hasholzner, Bernhard Rohfleisch, Christian Haubelt, Jürgen Teich. 346-351 [doi]
- Runtime power estimator calibration for high-performance microprocessorsHai Wang, Sheldon X.-D. Tan, Xuexin Liu, Ashish Gupta 0007. 352-357 [doi]
- Estimation based power and supply voltage management for future RF-powered multi-core smart cardsNorbert Druml, Christian Steger, Reinhold Weiss, Andreas Genser, Josef Haid. 358-363 [doi]
- Application-specific memory partitioning for joint energy and lifetime optimizationHaroon Mahmood, Massimo Poncino, Mirko Loghi, Enrico Macii. 364-369 [doi]
- State-of-the-art tools and techniques for quantitative modeling and analysis of embedded systemsMarius Bozga, Alexandre David, Arnd Hartmanns, Holger Hermanns, Kim G. Larsen, Axel Legay, Jan Tretmans. 370-375 [doi]
- Hybrid source-level simulation of data caches using abstract cache modelsStefan Stattelmann, Gernot Gebhard, Christoph Cullmann, Oliver Bringmann, Wolfgang Rosenstiel. 376-381 [doi]
- Accurate source-level simulation of embedded software with respect to compiler optimizationsZhonglei Wang, Jörg Henkel. 382-387 [doi]
- Scheduling for register file energy minimization in explicit datapath architecturesDongrui She, Yifan He, Bart Mesman, Henk Corporaal. 388-393 [doi]
- Multi-objective aware extraction of task-level parallelism using genetic algorithmsDaniel Cordes, Peter Marwedel. 394-399 [doi]
- RTL analysis and modifications for improving at-speed testKai-Hui Chang, Hong-Zu Chou, Igor L. Markov. 400-405 [doi]
- Test generation for clock-domain crossing faults in integrated circuitsNaghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil. 406-411 [doi]
- A new SBST algorithm for testing the register file of VLIW processorsDavide Sabena, Matteo Sonza Reorda, Luca Sterpone. 412-417 [doi]
- On the optimality of K longest path generation algorithm under memory constraintsJie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian. 418-423 [doi]
- Embedded systems and software challenges in electric vehiclesSamarjit Chakraborty, Martin Lukasiewycz, Christian Buckl, Suhaib A. Fahmy, Naehyuck Chang, Sangyoung Park, Younghyun Kim, Patrick Leteinturier, Hans Adlkofer. 424-429 [doi]
- Accelerators and emulators: Can they become the platform of choice for hardware verification?Bashir M. Al-Hashimi, Ronny Morad. 430 [doi]
- A closed-loop system for artifact mitigation in ambulatory electrocardiogram monitoringMohammed Shoaib, Gene Marsh, Harinath Garudadri, Somdeb Majumdar. 431-436 [doi]
- Enabling advanced inference on sensor nodes through direct use of compressively-sensed signalsMohammed Shoaib, Niraj K. Jha, Naveen Verma. 437-442 [doi]
- A multi-parameter bio-electric ASIC sensor with integrated 2-wire data transmission protocol for wearable healthcare systemGeng Yang, Jian Chen, Fredrik Jonsson, Hannu Tenhunen, Li-Rong Zheng. 443-448 [doi]
- Energy-efficient branch prediction with Compiler-guided History StackMingxing Tan, Xianhua Liu, Zichao Xie, Dong Tong, Xu Cheng. 449-454 [doi]
- Toward virtualizing branch direction predictionMaryam Sadooghi-Alvandi, Kaveh Aasaraai, Andreas Moshovos. 455-460 [doi]
- S/DC: A storage and energy efficient data prefetcherXianglei Dang, Xiaoyin Wang, Dong Tong, Junlin Lu, Jiangfang Yi, Keyi Wang. 461-466 [doi]
- An architecture-level approach for mitigating the impact of process variations on extensible processorsMehdi Kamal, Ali Afzali-Kusha, Saeed Safari, Massoud Pedram. 467-472 [doi]
- PCASA: Probabilistic control-adjusted Selective Allocation for shared cachesKonstantinos Aisopos, Jaideep Moses, Ramesh Illikkal, Ravishankar Iyer, Donald Newell. 473-478 [doi]
- Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicoresAbhishek Das, Matthew Schuchhardt, Nikos Hardavellas, Gokhan Memik, Alok N. Choudhary. 479-484 [doi]
- Dynamic cache management in multi-core architectures through run-time adaptationFazal Hameed, Lars Bauer, Jörg Henkel. 485-490 [doi]
- Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCsJosé L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini. 491-496 [doi]
- Preemption delay analysis for floating non-preemptive region schedulingJosé Marinho, Vincent Nélis, Stefan M. Petters, Isabelle Puaut. 497-502 [doi]
- Harmonic semi-partitioned scheduling for fixed-priority real-time tasks on multi-core platformMing Fan, Gang Quan. 503-508 [doi]
- Static scheduling of a Time-Triggered Network-on-Chip based on SMT solvingJia Huang, Jan Olaf Blech, Andreas Raabe, Christian Buckl, Alois Knoll. 509-514 [doi]
- Formal analysis of sporadic overload in real-time systemsSophie Quinton, Matthias Hanke, Rolf Ernst. 515-520 [doi]
- Error patterns in MLC NAND flash memory: Measurement, characterization, and analysisYu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai. 521-526 [doi]
- Modeling and testing of interference faults in the nano NAND Flash memoryJin Zha, Xiaole Cui, Chung-Len Lee. 527-531 [doi]
- Impact of resistive-open defects on the heat current of TAS-MRAM architecturesJ. Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, G. Prenat, Jérémy Alvarez-Herault, Ken Mackay. 532-537 [doi]
- Worst-case delay analysis of Variable Bit-Rate flows in network-on-chip with aggregate schedulingFahimeh Jafari, Axel Jantsch, Zhonghai Lu. 538-541 [doi]
- Dynamic-priority arbiter and multiplexer soft macros for on-chip networks switchesGiorgos Dimitrakopoulos, Emmanouil Kalligeros. 542-545 [doi]
- Low power aging-aware register file design by duty cycle balancingShuai Wang, Tao Jin, Chuanlei Zheng, Guangshan Duan. 546-549 [doi]
- PowerAdviser: An RTL power platform for interactive sequential optimizationsNainala Vyagrheswarudu, Subrangshu Das, Abhishek Ranjan. 550-553 [doi]
- Towards parallel execution of IEC 61131 industrial cyber-physical systems applicationsArquimedes Canedo, Mohammad Abdullah Al Faruque. 554-557 [doi]
- A scan pattern debugger for partial scan industrial designsKameshwar Chandrasekar, Supratik K. Misra, Sanjay Sengupta, Michael S. Hsiao. 558-561 [doi]
- FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUsNicola Bombieri, Franco Fummi, Valerio Guarnieri. 562-565 [doi]
- Exploiting binary translation for fast ASIP design space exploration on FPGAsSebastiano Pomata, Paolo Meloni, Giuseppe Tuveri, Luigi Raffo, Menno Lindwer. 566-569 [doi]
- Design of a low-energy data processing architecture for WSN nodesCedric Walravens, Wim Dehaene. 570-573 [doi]
- Application-specific power-efficient approach for reducing register file vulnerabilityHamed Tabkhi, Gunar Schirner. 574-577 [doi]
- On-line scheduling of target sensitive periodic tasks with the gravitational task modelRaphael Guerra, Gerhard Fohler. 578-581 [doi]
- Online scheduling for multi-core shared reconfigurable fabricLiang Chen, Thomas Marconi, Tulika Mitra. 582-585 [doi]
- SCFIT: A FPGA-based fault injection technique for SEU fault modelAbbas Mohammadi 0001, Mojtaba Ebrahimi, Alireza Ejlali, Seyed Ghassem Miremadi. 586-589 [doi]
- Research and innovation on Advanced Computing - an EU perspectiveThierry Van der Pyl. 591 [doi]
- Memristor technology in future electronic system designRonald Tetzlaff, Andreas Bruening. 592 [doi]
- TempoMP: Integrated prediction and management of temperature in heterogeneous MPSoCsShervin Sharifi, Raid Zuhair Ayoub, Tajana Simunic Rosing. 593-598 [doi]
- Thermal balancing of liquid-cooled 3D-MPSoCs using channel modulationMohamed M. Sabry, Arvind Sridhar, David Atienza. 599-604 [doi]
- Statistical thermal modeling and optimization considering leakage power variationsDa-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang. 605-610 [doi]
- Analysis and runtime management of 3D systems with stacked DRAM for boosting energy efficiencyJie Meng, Ayse Kivilcim Coskun. 611-616 [doi]
- A guiding coverage metric for formal verificationFinn Haedicke, Daniel Große, Rolf Drechsler. 617-622 [doi]
- Verification of partial designs using incremental QBF solvingPaolo Marin, Christian Miller, Matthew D. T. Lewis, Bernd Becker. 623-628 [doi]
- Non-solution implications using reverse domination in a modern SAT-based debugging environmentBao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris. 629-634 [doi]
- Optimizing performance analysis for synchronous dataflow graphs with shared resourcesDaniel Thiele, Rolf Ernst. 635-640 [doi]
- Compositional system-level design exploration with planning of high-level synthesisHung-Yi Liu, Michele Petracca, Luca P. Carloni. 641-646 [doi]
- Correct-by-construction multi-component SoC designRoopak Sinha, Partha S. Roop, Zoran Salcic, Samik Basu. 647-652 [doi]
- Model checking of Scenario-Aware Dataflow with CADPBart D. Theelen, Joost-Pieter Katoen, Hao Wu. 653-658 [doi]
- An instruction scratchpad memory allocation for the precision timed architectureAayush Prakash, Hiren D. Patel. 659-664 [doi]
- Bounding WCET of applications using SDRAM with Priority Based Budget Scheduling in MPSoCsHardik Shah, Andreas Raabe, Alois Knoll. 665-670 [doi]
- Time analysable synchronisation techniques for parallelised hard real-time applicationsMike Gerdes, Florian Kluge, Theo Ungerer, Christine Rochange, Pascal Sainrat. 671-676 [doi]
- Design for test and reliability in ultimate CMOSMichael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky. 677-682 [doi]
- Optimal energy management and recovery for FEVKosmas Knoedler, Jochen Steinmann, Sylvain Laversanne, Stephen Jones, Arno Huss, Emre Kural, David Sanchez, Oliver Bringmann, Jochen Zimmermann. 683-684 [doi]
- Virtual platforms: Breaking new groundsRainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel. 685-690 [doi]
- An FPGA-based accelerator for cortical object classificationMi Sun Park, Srinidhi Kestur, Jagdish Sabarad, Vijaykrishnan Narayanan, Mary Jane Irwin. 691-696 [doi]
- Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length CodingMuhammad Shafique, Bruno Zatt, Semeen Rehman, Florian Kriebel, Jörg Henkel. 697-702 [doi]
- Towards accurate hardware stereo correspondence: A real-time FPGA implementation of a segmentation-based adaptive support weight algorithmChristos Ttofis, Theocharis Theocharides. 703-708 [doi]
- An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemesGeorgios Chatziparaskevas, Andreas Brokalakis, Ioannis Papaefstathiou. 709-714 [doi]
- A SAT-based fitness function for evolutionary optimization of polymorphic circuitsLukás Sekanina, Zdenek Vasícek. 715-720 [doi]
- Mach-Zehnder interferometer based design of all optical reversible binary adderSaurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan. 721-726 [doi]
- Weighted area technique for electromechanically enabled logic computation with cantilever-based NEMS switchesShruti Patil, Min-Woo Jang, Chia-Ling Chen, DongJin Lee, Zhijang Ye, Walter E. Partlo, David J. Lilja, Stephen A. Campbell, Tianhong Cui. 727-732 [doi]
- Response-surface-based design space exploration and optimisation of wireless sensor nodes with tunable energy harvestersLeran Wang, Tom J. Kazmierski, Bashir M. Al-Hashimi, Mansour Aloufi, Joseph Wenninger. 733-738 [doi]
- Holistic modeling of embedded systems with multi-discipline feedback: Application to a Precollision Mitigation Braking SystemAntoine Lévêque, François Pêcheux, Marie-Minerve Louërat, Hassan Aboushady, Fabio Cenni, Serge Scotti, Abdelbasset Massouri, Laurent Clavier. 739-744 [doi]
- Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selectionElie Maricau, Dimitri de Jonghe, Georges G. E. Gielen. 745-750 [doi]
- A fast analog circuit yield estimation method for medium and high dimensional problemsBo Liu, Jarir Messaoudi, Georges G. E. Gielen. 751-756 [doi]
- Fast isomorphism testing for a graph-based analog circuit synthesis frameworkMarkus Meissner, Oliver Mitea, Linda Luy, Lars Hedrich. 757-762 [doi]
- Design of streaming applications on MPSoCs using abstract clocksAbdoulaye Gamatié. 763-768 [doi]
- SPDF: A schedulable parametric data-flow MoCPascal Fradet, Alain Girault, Peter Poplavkoy. 769-774 [doi]
- Modeling static-order schedules in synchronous dataflow graphsMorteza Damavandpeyma, Sander Stuijk, Twan Basten, Marc Geilen, Henk Corporaal. 775-780 [doi]
- Design space pruning through hybrid analysis in system-level design space explorationRoberta Piscitelli, Andy D. Pimentel. 781-786 [doi]
- Test pin count reduction for NoC-based Test delivery in multicore SOCsMichael Richter, Krishnendu Chakrabarty. 787-792 [doi]
- On effective TSV repair for 3D-stacked ICsLi Jiang, Qiang Xu, Bill Eklow. 793-798 [doi]
- DfT schemes for resistive open defects in RRAMsNor Zaidi Haron, Said Hamdioui. 799-804 [doi]
- Timing Modeling with AUTOSAR - Current state and future directionsMarie-Agnès Peraldi-Frati, Hans Blom, Daniel Karlsson, Stefan Kuntz. 805-809 [doi]
- Challenges and new trends in probabilistic timing analysisSophie Quinton, Rolf Ernst, Dominique Bertrand, Patrick Meumeu Yomsi. 810-815 [doi]
- QBf-based boolean function bi-decompositionHuan Chen 0001, Mikolás Janota, João Marques-Silva. 816-819 [doi]
- Automatic transition between structural system views in a safety relevant embedded systems development processChristian Ellen, Christoph Etzien, Markus Oertel. 820-823 [doi]
- Towards new applications of multi-function logic: Image multi-filteringLukás Sekanina, Vojtech Salajka. 824-827 [doi]
- Memory-map selection for firm real-time SDRAM controllersSven Goossens, Tim Kouters, Benny Akesson, Kees Goossens. 828-831 [doi]
- Real-time implementation and performance optimization of 3D sound localization on GPUsYun Liang, Zheng Cui, Shengkui Zhao, Kyle Rupnow, Yihao Zhang, Douglas L. Jones, Deming Chen. 832-835 [doi]
- Impact of TSV area on the dynamic range and frame rate performance of 3D-integrated image sensorsAdi Xhakoni, David San Segundo Bello, Georges G. E. Gielen. 836-839 [doi]
- Minimizing the latency of quantum circuits during mapping to the ion-trap circuit fabricMohammad Javad Dousti, Massoud Pedram. 840-843 [doi]
- Voltage propagation method for 3-D power grid analysisCheng Zhang, Vasilis F. Pavlidis, Giovanni De Micheli. 844-847 [doi]
- Yield optimization for radio frequency receiver at system levelSergey A. Nazin, Dominique Morche, Alexandre Reinhardt. 848-851 [doi]
- Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approachXuexin Liu, Sheldon X.-D. Tan, Hai Wang. 852-857 [doi]
- Automated critical device identification for configurable analogue transistorsRobert Rudolf, Pouya Taatizadeh, Reuben Wilcock, Peter R. Wilson. 858-861 [doi]
- Analysis of multi-domain scenarios for optimized dynamic power management strategiesJochen Zimmermann, Oliver Bringmann, Wolfgang Rosenstiel. 862-865 [doi]
- PUF-based secure test wrapper design for cryptographic SoC testingAmitabh Das, Ünal Koçabas, Ahmad-Reza Sadeghi, Ingrid Verbauwhede. 866-869 [doi]
- Complexity, quality and robustness - the challenges of tomorrow's automotive electronicsUlrich Abelein, Helmut Lochner, Daniel Hahn, Stefan Straube. 870-871 [doi]
- Measuring and improving the robustness of automotive smart power microelectronicsThomas Nirmaier, Volker Meyer zu Bexten, Markus Tristl, Manuel Harrant, Matthias Kunze, Monica Rafaila, Julia Lau, Georg Pelz. 872-873 [doi]
- Panel: What is EDA doing for trailing edge technologies?Marco Casale-Rossi, Pierluigi Rolandi, Andreas Bruening, Antun Domic, Rainer Kress, Joseph Sawicki, Christian Sebeke. 874 [doi]
- Reli: Hardware/software Checkpoint and Recovery scheme for embedded processorsTuo Li 0001, Roshan G. Ragel, Sri Parameswaran. 875-880 [doi]
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- Efficient Gröbner basis reductions for formal verification of galois field multipliersJinpeng Lv, Priyank Kalla, Florian Enescu. 899-904 [doi]
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- Formal methods for ranking counterexamples through assumption miningSrobona Mitra, Ansuman Banerjee, Pallab Dasgupta. 911-916 [doi]
- Transistor-level gate model based statistical timing analysis considering correlationsQin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs. 917-922 [doi]
- Current source modeling for power and timing analysis at different supply voltagesChristoph Knoth, Hela Jedda, Ulf Schlichtmann. 923-928 [doi]
- Clock skew scheduling for timing speculationRong Ye, Feng Yuan, Hai Zhou, Qiang Xu. 929-934 [doi]
- Robust and flexible mapping for real-time distributed applications during the early design phasesJunhe Gan, Paul Pop, Flavius Gruian, Jan Madsen. 935-940 [doi]
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- Co-design techniques for distributed real-time embedded systems with communication security constraintsKe Jiang, Petru Eles, Zebo Peng. 947-952 [doi]
- Logic encryption: A fault analysis perspectiveJeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri. 953-958 [doi]
- Low-cost implementations of on-the-fly tests for random number generatorsFilip Veljkovic, Vladimir Rozic, Ingrid Verbauwhede. 959-964 [doi]
- Post-deployment trust evaluation in wireless cryptographic ICsYier Jin, Dzmitry Maliuk, Yiorgos Makris. 965-970 [doi]
- Batteries and battery management systems for electric vehiclesM. Brandl, H. Gall, M. Wenger, V. Lorentz, M. Giegerich, Federico Baronti, Gabriele Fantechi, Luca Fanucci, Roberto Roncella, Roberto Saletti, Sergio Saponara, A. Thaler, M. Cifrain, W. Prochazka. 971-976 [doi]
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- Multi-core architecture design for ultra-low-power wearable health monitoring systemsAhmed Yasir Dogan, Jeremy Constantin, Martino Ruggiero, Andreas Burg, David Atienza. 988-993 [doi]
- Reducing the energy cost of computing through efficient co-scheduling of parallel workloadsCan Hankendi, Ayse Kivilcim Coskun. 994-999 [doi]
- SAFER PATH: Security architecture using fragmented execution and replication for protection against trojaned hardwareMark R. Beaumont, Bradley D. Hopkins, Tristan Newby. 1000-1005 [doi]
- ASIC implementations of five SHA-3 finalistsXu Guo, Meeta Srivastav, Sinan Huang, Dinesh Ganta, Michael B. Henry, Leyla Nazhandali, Patrick Schaumont. 1006-1011 [doi]
- Side channel analysis of the SHA-3 finalistsMichael Zohner, Michael Kasper, Marc Stöttinger, Sorin A. Huss. 1012-1017 [doi]
- Combining module selection and replication for throughput-driven streaming programsJason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou. 1018-1023 [doi]
- Exploiting area/delay tradeoffs in high-level synthesisAlex Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori Watanabe. 1024-1029 [doi]
- Predicting best design trade-offs: A case study in processor customizationMarcela Zuluaga, Edwin V. Bonilla, Nigel P. Topham. 1030-1035 [doi]
- Automatic design of low-power encoders using reversible circuit synthesisRobert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz. 1036-1041 [doi]
- Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAMVibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene. 1042-1047 [doi]
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- MAPG: Memory access power gatingKwangok Jeong, Andrew B. Kahng, Seokhyeong Kang, Tajana Simunic Rosing, Richard D. Strong. 1054-1059 [doi]
- State of health aware charge management in hybrid electrical energy storage systemsQing Xie, Xue Lin, Yanzhi Wang, Massoud Pedram, Donghwa Shin, Naehyuck Chang. 1060-1065 [doi]
- Automated construction of a cycle-approximate transaction level model of a memory controllerVladimir Todorov, Daniel Mueller-Gritschneder, Helmut Reinig, Ulf Schlichtmann. 1066-1071 [doi]
- Refinement of UML/MARTE models for the design of networked embedded systemsEmad Samuel Malki Ebeid, Franco Fummi, Davide Quaglia, Francesco Stefanni. 1072-1077 [doi]
- Debugging of inconsistent UML/OCL modelsRobert Wille, Mathias Soeken, Rolf Drechsler. 1078-1083 [doi]
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- Testing RF circuits with true non-intrusive built-in sensorsLouay Abdallah, Haralampos-G. D. Stratigopoulos, Salvador Mir, Josep Altet. 1090-1095 [doi]
- Monitoring active filters under automotive aging scenarios with embedded instrumentJinbo Wan, Hans G. Kerkhoff. 1096-1101 [doi]
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- Probabilistic response time bound for CAN messages with arbitrary deadlinesPhilip Axer, Maurice Sebastian, Rolf Ernst. 1114-1117 [doi]
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- Static analysis of asynchronous clock domain crossingsShubhyant Chaturvedi. 1122-1125 [doi]
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- Revealing side-channel issues of complex circuits by enhanced leakage modelsAnnelie Heuser, Werner Schindler, Marc Stöttinger. 1179-1184 [doi]
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- Multi-token resource sharing for pipelined asynchronous systemsJohn Hansen, Montek Singh. 1191-1196 [doi]
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- An efficient framework for passive compact dynamical modeling of multiport linear systemsZohaib Mahmood, Roberto Suaya, Luca Daniel. 1203-1208 [doi]
- Analysis and design of sub-harmonically injection locked oscillatorsArkosnato Neogy, Jaijeet S. Roychowdhury. 1209-1214 [doi]
- nd-order noise shapingPeng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen. 1215-1220 [doi]
- Large signal simulation of integrated inductors on semi-conducting substratesWim Schoenmaker, Michael Matthes, Bart De Smedt, Sascha Baumanns, Caren Tischendorf, Rick Janssen. 1221-1226 [doi]
- Time-triggered implementations of mixed-criticality automotive softwareDip Goswami, Martin Lukasiewycz, Reinhard Schneider 0001, Samarjit Chakraborty. 1227-1232 [doi]
- Timing analysis of cyber-physical applications for hybrid communication protocolsAlejandro Masrur, Dip Goswami, Samarjit Chakraborty, Jian-Jia Chen, Anuradha Annaswamy, Ansuman Banerjee. 1233-1238 [doi]
- A cyberphysical synthesis approach for error recovery in digital microfluidic biochipsYan Luo, Krishnendu Chakrabarty, Tsung-Yi Ho. 1239-1244 [doi]
- Predictive control of networked control systems over differentiated services lossy networksRiccardo Muradore, Davide Quaglia, Paolo Fiorini. 1245-1250 [doi]
- Input vector monitoring on line concurrent BIST based on multilevel decoding logicIoannis Voyiatzis. 1251-1256 [doi]
- High performance reliable variable latency carry select additionKai Du, Peter J. Varman, Kartik Mohanram. 1257-1262 [doi]
- Salvaging chips with caches beyond repairHsunwei Hsiung, Byeongju Cha, Sandeep K. Gupta. 1263-1268 [doi]
- Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanismsKai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang. 1269-1274 [doi]
- Moore meets maxwellRaul Camposano, Dipanjan Gope, Stefano Grivet-Talocia, Vikram Jandhyala. 1275-1276 [doi]
- Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICsErik Jan Marinissen. 1277-1282 [doi]
- A TDM NoC supporting QoS, multicast, and fast connection set-upRadu Stefan, Anca Mariana Molnos, Jude Angelo Ambrose, Kees Goossens. 1283-1288 [doi]
- Parallel probing: Dynamic and constant time setup procedure in circuit switching NoCShaoteng Liu, Axel Jantsch, Zhonghai Lu. 1289-1294 [doi]
- A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channelsZhiliang Qian, Ying Fei Teh, Chi-Ying Tsui. 1295-1300 [doi]
- Spintronic memristor based temperature sensor design with CMOS current referenceXiuyuan Bi, Chao Zhang, Hai Li, Yiran Chen, Robinson E. Pino. 1301-1306 [doi]
- 3D-FlashMap: A physical-location-aware block mapping strategy for 3D NAND flash memoryYi Wang 0003, Luis Angel D. Bathen, Zili Shao, Nikil D. Dutt. 1307-1312 [doi]
- Asymmetry of MTJ switching and its implication to STT-RAM designsYaojun Zhang, XiaoBin Wang, Yong Li 0009, Alex K. Jones, Yiran Chen. 1313-1318 [doi]
- Comparative analysis of SRAM memories used as PUF primitivesGeert Jan Schrijen, Vincent van der Leest. 1319-1324 [doi]
- Comparison of Self-Timed Ring and Inverter Ring Oscillators as entropy sources in FPGAsAbdelkarim Cherkaoui, Viktor Fischer, Alain Aubert, Laurent Fesquet. 1325-1330 [doi]
- A sensor-assisted self-authentication framework for hardware trojan detectionMin Li, Azadeh Davoodi, Mohammad Tehranipoor. 1331-1336 [doi]
- Towards improving simulation of analog circuits using model order reductionHenda Aridhi, Mohamed H. Zaki, Sofiène Tahar. 1337-1342 [doi]
- Efficiency evaluation of parametric failure mitigation techniques for reliable SRAM operationElena I. Vatajelu, Joan Figueras. 1343-1348 [doi]
- A GPU-accelerated envelope-following method for switching power converter simulationXuexin Liu, Sheldon X.-D. Tan, Hai Wang, Hao Yu. 1349-1354 [doi]
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- VLSI legalization with minimum perturbation by iterative augmentationUlrich Brenner. 1385-1390 [doi]
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- Mapping into LUT structuresSayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen. 1579-1584 [doi]
- Row-shift decompositions for index generation functionsTsutomu Sasao. 1585-1590 [doi]
- Custom on-chip sensors for post-silicon failing path isolation in the presence of process variationsMin Li, Azadeh Davoodi, Lin Xie. 1591-1596 [doi]
- On effective flip-chip routing via pseudo single redistribution layerHsin-Wu Hsu, Meng-Ling Chen, Hung-Ming Chen, Hung-Chun Li, Shi-Hao Chen. 1597-1602 [doi]
- AIR (Aerial Image Retargeting): A novel technique for in-fab automatic model-based retargeting-for-yieldAyman Yehia Hamouda, Mohab Anis, Karim S. Karim. 1603-1608 [doi]
- Layout-Driven Robustness Analysis for misaligned Carbon Nanotubes in CNTFET-based standard cellsMatthias Beste, Mehdi Baradaran Tahoori. 1609-1614 [doi]
- Advances in variation-aware modeling, verification, and testing of analog ICsDimitri de Jonghe, Elie Maricau, Georges G. E. Gielen, Trent McConaghy, Bratislav Tasic, Haralampos-G. D. Stratigopoulos. 1615-1620 [doi]