Abstract is missing.
- OK, If These CAD Tools Are So Great, Why Isn t My Chip Design On Schedule?Neil Weste. 2-8
- The Future of Programmable Logic and Its Impact on Digital System DesignWilliam S. Carter. 10-16
- Emerging Techologies for Electronic Design and TestPrathima Agrawal. 18
- Grammar-Based Optimization of Synthesis ScenariosAndreas Kuehlmann, Lukas P. P. P. van Ginneken. 20-25
- Architecture Oriented Logic Optimization for Lookup Table Based FPGAsAiguo Lu, Jonathan Saul, Erik L. Dagless. 26-29
- FPGA Synthesis Using Function DecompositionYung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram. 30-35
- Efficent Boolean Matching Algorithm for Cell LibrariesQinghong Wu, C. Y. Roger Chen, John M. Acken. 36-39
- A Superassociative Tagged Cache Coherence DirectoryDavid J. Lilja, Shanthi Ambalavanan. 42-45
- Issues in Multi-Level Cache DesignsLishing Liu. 46-52
- Analysis of Multiprocessor Memory Refernce BehaviorJeffrey D. Gee, Alan Jay Smith. 53-59
- Determination of Optimal Sizes for a First and Second Level SRAM-DRAM On-Chip Cache CombinationRupinder Hundal, Vojin G. Oklobdzija. 60-64
- Design and Evaluation of the High Performance Multi-Processor ServerM. Morioka, K. Kurosawa, S. Miura, T. Nakamikawa, S. Ishikawa. 66-69
- A Massively Parallel Multithreaded Architecture: DAVRIDSangho Ha, Junghwan Kim, Eunha Rho, Yoonhee Nah, Sangyong Han, Daejoon Hwang, Heunghwan Kim, Seung Ho Cho. 70-74
- Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path LengthsHussain Al-Asaad, Mankuan Michael Vai, James Feldman. 75-78
- Fault Tolerant Processor Arrays for Nonlinear Shortest Path ProblemChoong Gun Oh, Hee Yong Youn. 79-83
- Delay-Verifiability of Combinational Circuits Based on Primitive FaultsWuudiann Ke, Premachandran R. Menon. 86-90
- Behavioral Synthesis for Hierarchical Testability of Controller/Data Path Circuits with Conditional BranchesSandeep Bhatia, Niraj K. Jha. 91-96
- Testability ConsiderationsShangzhi Sun, David Hung-Chang Du, Duen-Ren Liu. 97-100
- SYNCBIST: SYNthesis for Concurrent Built-In-Self-TestabilityIan G. Harris, Alex Orailoglu. 101-104
- OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic AlgorithmsBernd Becker, Rolf Drechsler. 106-110
- Tradeoffs in Canonical Sequential Function RepresentationsAarti Gupta, Allan L. Fisher. 111-116
- Capturing Synchronization Specifications for Sequential CompositionsZheng Zhu, Steven D. Johnson. 117-121
- Concurrent Error Detection in High Speed Carry-free Division Using Alternative Input DataChin-Long Wey. 124-127
- Design of TSC Code-Disjoint Inverter-Free PLA s for Separable Unordered CodesStanislaw J. Piestrak. 128-131
- On-Chip TEC-QED ECC for Ultra-Large, Single-Chip Memory SystemsFahad M. Alzahrani, Tom Chen. 132-137
- Dynamic List-Scheduling with Finite ResourcesRay A. Kamin III, George B. Adams III, Pradeep K. Dubey. 140-144
- PRISC Software Acceleration TechniquesRahul Razdan, Karl S. Brace, Michael D. Smith. 145-149
- Communication Sensitive Rotation SchedulingSissades Tongsima, Nelson L. Passos, Edwin Hsing-Mean Sha. 150-153
- Efficient Timing Analysis for CMOS Circuits Considering Data Dependent DelaysShangzhi Sun, David Hung-Chang Du, Hsi-Chuan Chen. 156-159
- Short Destabilizing Paths in Timing VerificationRafael Peset Llopis, Lluis Ribas, Jordi Carrabina. 160-163
- Synchronization of Wave-Pipelined CircuitsXuguang Zhang, Ramalingam Sridhar. 164-167
- Mesh Routing Topologies for Multi-FPGA SystemsScott Hauck, Gaetano Borriello, Carl Ebeling. 170-177
- PROTEUS: Programmable Hardware for Telecommunication SystemsNaohisa Ohta, Hiroshi Nakada, Kazuhisa Yamada, Akihiro Tsutsui, Toshiaki Miyazaki. 178-183
- Area & Time Limitations of FPGA-based Virtual HardwareOsama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke. 184-189
- AS/400:::TM::: 64-bit PowerPC:::TM:::-Compatible Processor ImplementaitonJohn M. Borkenhagen, Glen H. Handlogten, John D. Irish, Sheldon B. Levenstein. 192-196
- AS/400 PowerPC:::TM::: Compatible Semi-Custom TechnologyMike Gruver, Nghia Phan, Tony Aipperspach, Scott Hilker, Jerry Bartley. 197-202
- A 32-bit Superscalar Microprocessor with 64-Bit Processing and High Bandwidth DRAM InterfaceMasahito Matsuo, Hiroyuki Kondo, Yukari Takata, Souichi Kobayashi, Mitsugu Satoh, Toyohiko Yoshida, Yuichi Saitoh, Jun-ichi Hinata. 203-210
- Area Efficient Synthesis of Asynchronous Interface CircuitsRuchir Puri, Jun Gu. 212-216
- The Design and Evaluation of an Asynchronous MicroprocessorStephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, J. V. Woods. 217-220
- Performance Analysis and Optimization of Asynchronous CircuitsPrabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella. 221-224
- Automatic Verification of RefinementTrevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger. 225-229
- Efficient State Space Pruning in Symbolic Backward TraversalGianpiero Cabodi, Paolo Camurati, Stefano Quer. 230-235
- A Structural Approach to State Space Decomposition for Approximate Reachability AnalysisHyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi. 236-239
- An Exact Optimization of Two-Level Acyclic Sequential CircuitsEllen Sentovich, Robert K. Brayton. 242-249
- State Assignment for Power and Area MinimizationKuo-Hua Wang, Wen-Sing Wang, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin. 250-254
- Minimizing Interacting Finite State Machines: A Compositional Approach to Language to ContainmentAdnan Aziz, Vigyan Singhal, Gitanjali Swamy, Robert K. Brayton. 255-261
- Continuations in Hardware-Software CodesignM. Esen Tuna, Steven D. Johnson, Robert G. Burger. 264-269
- Compression of Embedded System ProgramsMichael Kozuch, Andrew Wolfe. 270-277
- HW/SW Codesign for Embedded Telecom SystemsStefano Antoniazzi, Alessandro Balboni, William Fornaciari, Donatella Sciuto. 278-281
- A Signature Analyzer for Analog and Mixed-signal CircuitsNaveena Nagi, Abhijit Chatterjee, Jacob A. Abraham. 284-287
- WRAPTure: A Tool for Evaluation and Optimization of Weights for Weighted Random Pattern TestingAmitava Majumdar. 288-291
- A Class of Good Characteristics Polynomials for LFSR Test Pattern GeneratorsDimitrios Kagaris, Spyros Tragoudas. 292-295
- A Parallel CMOS 2 s Complement Multiplier Based on 5: 3 CounterZ. Guan, P. Thomson, A. E. A. Almaini. 298-301
- A New Asynchronous Multiplier Using Enable/Disable CMOS Differential LogicEdwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham. 302-305
- An Arbitration Tree Adapted to Object Oriented Associative MemoriesDenis Archambaud, Pascal Faudemay. 306-310
- Write Buffer Design for On-Chip CachePong P. Chu, Ramana Gottipati. 311-316
- Behavioral Synthesis for low PowerAnand Raghunathan, Niraj K. Jha. 318-322
- Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI DesignsLaurence Goodby, Alex Orailoglu, Paul M. Chau. 323-326
- Allocation and Binding During Fault-Secure Microarchitecture SynthesisSergei Sokolov, Ramesh Karri. 327-330
- Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering MicroarchitecturesKarin Högstedt, Alex Orailoglu. 331-334
- POWER2 Architecture and PerformanceE. L. Hannon, F. P. O Connell, L. J. Shieh. 336-339
- The Effects of Compiler Options on Application PerformanceKatherine E. Stewart, Steven W. White. 340-343
- Architectural Performance Verification: PowerPC:::TM::: ProcessorsS. Surya, Pradip Bose, Jacob A. Abraham. 344-347
- Testability Analysis for Test Generation in Synchronous Sequential CircuitsR. Wolber, Uwe Gläser, Heinrich Theodor Vierhaus. 350-353
- A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled CircuitsSanghyeon Baeg, William A. Rogers. 354-358
- Path-Delay Fault Simulation for a Standard Scan Design MethodologySungho Kang, Wai-On Law, Bill Underwood. 359-362
- Multifault Testable Circuits Based on Binary Parity DiagramsSandip Kundu. 363-366
- Two-phase Logic Design by Hardware FlowchartsKevin Covey, Sandra Murdock, Thomas R. Shiple. 368-380
- On Valid Clocking for Combinational CircuitsShangzhi Sun, David Hung-Chang Du, Yaun-chung Hsu, Hsi-Chuan Chen. 381-384
- Latch Design for Transient Pulse ToleranceHungse Cha, Janak H. Patel. 385-388
- Timing Verification and Optimization for the PowerPC:::TM::: Processor FamilyRobert E. Mains, Thomas A. Mosher, Lukas P. P. P. van Ginneken, Robert F. Damiano. 390-393
- On Retiming for FPGA Logic Module MinimizationYao-Ping Chen, D. F. Wong. 394-397
- Retiming for the Global Optimization of Synchronous Sequential CircuitsSamir Lejmi, Bozena Kaminska, Edouard Wagneur. 398-403
- The PowerPC:::TM::: 604 Microprocessor Design MethodologyCharles P. Roth, Ricky Lewelling, Timothy B. Brodnax. 404-408
- Single Chip PCI Bridge and Memory Controller for PowerPC:::TM::: MicroprocessorsMichael J. Garcia, Brian K. Reynolds. 409-412
- PowerPC Visual Simulator: Peeking Under the Hood of the PowerPC EngineM. Armstead, Michael Cogswell, S. Halverson, T. Musta. 413-418
- Fourier Transform based DS/FH Spread Spectrum ReceiverJack P. F. Glas, Sándor E. Skolnik. 420-423
- An FPGA based Configurable I/O System for AC Drive ControllersD. R. Woodward, D. C. Levy, R. G. Harley. 424-427
- Design of an Embedded Video Compression System - A Quantitative ApproachJörg Wilberg, Raul Camposano, Ursula Westerholz, Uwe Steinhausen. 428-431
- UCLOCK: Automated Design of High-Peformance Unclocked State MachinesSteven M. Nowick, Bill Coates. 434-441
- Peephole Optimization of Asynchronous Macromodule NetworksGanesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand. 442-446
- Initialization Isuues in the Synthesis of Asynchronous CircuitsSavita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan. 447-452
- Architectural Verification of Processors Using Symbolic Instruction GraphsAshok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen. 454-459
- A Parallel Method for Functional Verification of Medium and High Throughput DSP SynthesisMark Genoe, Luc J. M. Claesen, Hugo De Man. 460-463
- The Structured Logic CAD Suite Used on the DPS7000 SystemHuy Nam Nguyen, J. P. Tual, L. Ducousso, M. Thill, P. Vallet. 464-467
- Optimal Logic Blocks for FPGAs, using Factorial Design TechniquesFaisal Haq, Samiha Mourad. 470-474
- Routing Architectures for Hierarchical Field Programmable Gate ArraysAditya A. Aggarwal, David M. Lewis. 475-478
- Defect Tolerant SRAM Based FPGAsJason L. Kelly, Peter A. Ivey. 479-482
- Domain Based Testing: Increasing Test Case ReuseAnneliese Amschler Andrews, Richard T. Mraz, Jeff Walls, Pete Ocken. 484-491
- Software Metrics for Object-Oriented DesignsRaghu V. Hudli, Curtis L. Hoskins, Anand V. Hudli. 492-495
- Combinational Digit-Set Converters for Hybrid Radix-4 ArithmeticLuis A. Montalvo, Alain Guyot. 498-503
- A Self-Timed Divider Using RSD Number SystemKiyoung Choi, KiJong Lee, Jun-Woo Kang. 504-507
- Design of High-Speed Residue-to-Binary Number System Converter Based on Chinese Remainder TheoremStanislaw J. Piestrak. 508-511
- Complex Operator SynthesisMichael Quayle, ChiLai Huang. 514-517
- In the Driver s Seat of BooleDozerDaniel Brand, Robert F. Damiano, Lukas P. P. P. van Ginneken, Anthony D. Drumm. 518-521
- ASOP: Arithmetic Sum-of-Products GeneratorDileep Kumar, Bob Erickson. 522-526
- YEPHCAD and FLORA: Logic Synthesis for Control and DatapathH. Sato, Michihiro Yamazaki, Masahiro Fujita. 527-530
- Future Needs for Automotive ElectronicsPeter Thoma. 532-539
- A VLSI Chip for Template MatchingN. Ranganathan, Satish Venugopal. 542-545
- COBRA: An 1.2 Million Transistor Expandable Column FFT ChipGlen Sunada, Jain Jin, Matt Berzins, Tom Chen. 546-550
- A VLSI Priority Packet Queue with Overwrite and InheritanceDan Picker, Michael B. Bendak, Ronald D. Fellman. 551-555
- Domain Characterization of Transmission Line Models for Efficient SimulationRohini Gupta, Seok-Yoon Kim, Lawrence T. Pillage. 558-562
- Transient Analysis of VLSI Interconnects with Arbitrary Initial Distributions and Nonlinear TerminationsHong Liu, Fung-Yuel Chang, Omar Wing. 563-566
- Simulating Uniform Lossy Lines by the Time-Domain Modal AnalysisAli El-Zein, Monjurul Haque, Salim Chowdhury. 567-570
- A Multi-Schedule Approach to High-Level SynthesisMehmet Emin Dalkiliç, Vijay Pitchumani. 572-575
- Register Estimation from Behavioral SpecificationsAlok Sharma, Rajiv Jain. 576-580
- An ILP Solution for Simultaneous Scheduling, Allocation, and Binding in Multiple Block SynthesisThomas Charles Wilson, Gary William Grewal, Dilip K. Banerji. 581-586
- Optimal Datapath Synthesis of Partitioned Signal Processing Algorithm for Multiple FPGAsBaher Haroun, Behzard Sajjadi. 587-589
- Optimal Design of Self-Damped Lossy Transmission Lines for Multichip ModulesJimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai. 594-598
- Differential Routing of MCMs - CIF: The Ideal Bifurcation MediumJames Loy, Atul Garg, Mukkai S. Krishnamoorthy, John F. McDonald. 599-603
- Improved Techniques for MCM Layer AssignmentMohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia. 604-607
- Thermal Design of an Advanced Multichip Module for a RISC ProcessorAtul Garg, T.-L. Sham, Hans J. Greub, James Loy, Jack F. McDonald. 608-611
- Reducing Power Dissipation in Serially Connected MOSFET Circuits via Transistor ReorderingRazak Hossain, Menghui Zheng, Alexander Albicki. 614-617
- Improving CMOS Speed at Low Supply VoltagesHorng-Dar Lin, Ran-Hong Yan, Douglas Yu. 618-621
- Asymptotic Limits of Video Signal Processing ArchitecturesSantanu Dutta, Wayne Wolf. 622-625
- Techniques for Fast CMOS-based Conditional Sum AddersHans Lindkvist, Per Andersson. 626-635