Salvador Manich - researchr alias

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Viewing Publication 1 - 30 from 30

2023

True Random Number Generator Based on the Variability of the High Resistance State of RRAMsMaryam Akbari, Sattar Mirzakuchaki, Daniel Arumí, Salvador Manich, Álvaro Gómez-Pau, Francesca Campabadal, Mireia Bargallo González, Rosa Rodríguez-Montañés. access, 11:66682-66693, 2023. [doi]

2022

Influence of Punch Trough Stop Layer and Well Depths on the Robustness of Bulk FinFETs to Heavy Ions ImpactAntonio Calomarde, Salvador Manich, Antonio Rubio, Francisco Gámiz. access, 10:47169-47178, 2022. [doi]

On the Fitting and Improvement of RRAM Stanford-Based Model Parameters Using TiN/Ti/HfO2/W Experimental DataV. Mahboubi, Daniel Arumí, A. Gómez, R. Rodríguez, Salvador Manich. dcis 2022: 1-6 [doi]

2021

2019

A Calibratable Detector for Invasive AttacksMichael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich. tvlsi, 27(5):1067-1079, 2019. [doi]

2018

The Low Area Probing Detector as a Countermeasure Against Invasive AttacksMichael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl. tvlsi, 26(2):392-403, 2018. [doi]

2017

Defending cache memory against cold-boot attacks boosted by power or EM radiation analysisMadalin Neagu, Salvador Manich. mj, 62:85-98, 2017. [doi]

2016

RRAM based cell for hardware security applicationsDaniel Arumí, Salvador Manich, Rosa Rodríguez-Montañés. ivsw 2016: 1-6 [doi]

2015

Improving security in cache memory by power efficient scrambling techniqueMadalin-Ioan Neagu, Liviu Miclea, Salvador Manich. iet-cdt, 9(6):283-292, 2015. [doi]

2014

Interleaved scrambling technique: A novel low-power security layer for cache memoriesMadalin Neagu, Liviu Miclea, Salvador Manich. ets 2014: 1-2 [doi]

A Low Area Probing Detector for Power Efficient Security ICsMichael Weiner, Salvador Manich, Georg Sigl. rfidsec 2014: 185-197 [doi]

2013

A Highly Time Sensitive XOR Gate for Probe Attempt DetectorsSalvador Manich, Martin Strasser. tcas, 60-II(11):786-790, 2013. [doi]

Differential scan-path: A novel solution for secure design-for-testabilitySalvador Manich, Markus S. Wamser, Oscar M. Guillen, Georg Sigl. itc 2013: 1-9 [doi]

2012

Detection of probing attempts in secure ICsSalvador Manich, Markus S. Wamser, Georg Sigl. host 2012: 134-139 [doi]

2010

Design and implementation of Automatic Test Equipment IP moduleS. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich. ets 2010: 244 [doi]

2007

Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory ResourcesSalvador Manich, L. Garcia-Deiros, Joan Figueras. tcad, 26(11):2046-2058, 2007. [doi]

2004

BIST Technique by Equally Spaced Test Vector SequencesSalvador Manich, L. García, L. Balado, E. Lupon, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras. vts 2004: 206-216 [doi]

On High-Quality, Low Energy Built-In Self Test Preparation at RT-LevelMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, L. Balado, Joan Figueras. et, 20(4):345-355, 2004. [doi]

2003

On the selection of efficient arithmetic additive test pattern generators [logic test]Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius, R. Rodriguez, Joan Figueras. ets 2003: 9-14 [doi]

Power and Energy Consumption of CMOS Circuits: Measurement Methods and Experimental ResultsJosep Rius, Alejandro Peidro, Salvador Manich, Rosa Rodriguez-Sánchez. patmos 2003: 80-89 [doi]

2002

On High-Quality, Low Energy BIST Preparation at RT-LevelMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001, Salvador Manich, Luz Balado, Joan Figueras. latw 2002: 52-57

RTL Level Preparation of High-Quality/Low-Energy/Low-Power BISTMarcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras. itc 2002: 814-823 [doi]

2000

Low Power BIST by Filtering Non-Detecting VectorsSalvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, P. Teixeira, M. Santos. et, 16(3):193-202, 2000. [doi]

1999

1997

Maximizing the weighted switching activity in combinational CMOS circuits under the variable delay modelSalvador Manich, Joan Figueras. date 1997: 597-602 [doi]

Fault-Secure Parity Prediction Arithmetic OperatorsMichael Nicolaidis, Ricardo de Oliveira Duarte, Salvador Manich, Joan Figueras. dt, 14(2):60-71, 1997. [doi]

1996

Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoringSalvador Manich, Michael Nicolaidis, Joan Figueras. vts 1996: 124-129 [doi]

Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and ImplementationsMichael Nicolaidis, Salvador Manich, Joan Figueras. date 1996: 186-194 [doi]

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