Wei Zhang 0012 - researchr alias

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2024

Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical DataJiandong Mu, Mengdi Wang, Feiwen Zhu, Jun Yang, Wei Lin 0016, Wei Zhang 0012. tcad, 43(2):548-561, February 2024. [doi]

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection NetworkChunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang 0012. fpga 2024: 143-153 [doi]

2023

Special Issue: "AI Acceleration on FPGAs"Yun Liang 0001, Wei Zhang 0012, Stephen Neuendorffer, Wayne Luk. tecs, 22(6), November 2023. [doi]

PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture SearchAfzal Ahmad, Zhiyao Xie, Wei Zhang 0012. dac 2023: 1-6 [doi]

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAsLinfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang 0012. fpga 2023: 15-25 [doi]

Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEsZili Kou, Sharad Sinha, Wenjian He, Wei Zhang 0012. date 2023: 1-6 [doi]

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLSZhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang 0012. tcad, 42(11):3925-3938, November 2023. [doi]

Accelerating Loop-Oriented RTL Simulation With Code InstrumentationFubing Mao, Yapu Guo, Xiaofei Liao, Hai Jin 0001, Wei Zhang 0012, Haikun Liu, Long Zheng 0003, Xu Liu, Zihan Jiang, Xiaohua Zheng. tcad, 42(12):4985-4998, December 2023. [doi]

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNNJian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang 0012. dac 2023: 1-6 [doi]

Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic TransformYuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang 0012. fccm 2023: 174-183 [doi]

2021

2020

BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block InformationWenjian He, Sanjeev Das, Wei Zhang 0012, Yang Liu 0003. tecs, 19(1), 2020. [doi]

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance ModelingJiandong Mu, Wei Zhang 0012, Hao Liang, Sharad Sinha. trets, 13(3), 2020. [doi]

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded ApplicationsJieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding 0001, Sharad Sinha, Wei Zhang 0012, Shaojie Shen. fpl 2020: 269-276 [doi]

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGAJieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang 0012, Yun Liang 0001, Bingsheng He. tcad, 39(7):1428-1441, 2020. [doi]

Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex ModelZuomin Zhu, Wei Zhang 0012, Vivek Chaturvedi, Amit Kumar Singh 0002. tcad, 39(3):686-699, 2020. [doi]

2019

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic PowerZhe Lin 0007, Sharad Sinha, Wei Zhang 0012. tcad, 38(9):1661-1674, 2019. [doi]

Editorial TVLSI Positioning - Continuing and Accelerating an Upward TrajectoryMassimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han 0001, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu 0001, Wei Zhang 0012, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber. tvlsi, 27(2):253-280, 2019. [doi]

A Cost-Effective CNN Accelerator Design with Configurable PU on FPGAChi Fung Brian Fong, Jiandong Mu, Wei Zhang 0012. isvlsi 2019: 31-36 [doi]

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level SynthesisTingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang 0012. iccad 2019: 1-6 [doi]

Accelerate pattern recognition for cyber security analysisMohammad Tahghighi, Wei Zhang 0012. aspdac 2019: 23-24 [doi]

2018

FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAsYun Liang 0001, Shuo Wang, Wei Zhang 0012. TC, 67(12):1750-1764, 2018. [doi]

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-ProcessorsZhe Lin 0007, Sharad Sinha, Hao Liang 0003, Liang Feng, Wei Zhang 0012. tmscs, 4(2):152-162, 2018. [doi]

Analyzing Data Cache Related Preemption Delay With Multiple PreemptionsWei Zhang 0012, Nan Guan, Lei Ju, Weichen Liu. tcad, 37(11):2255-2265, 2018. [doi]

Hi-DMM: High-Performance Dynamic Memory Management in High-Level SynthesisTingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang 0012. tcad, 37(11):2555-2566, 2018. [doi]

Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-ChipWeichen Liu, Lei Yang 0018, Weiwen Jiang, Liang Feng, Nan Guan, Wei Zhang 0012, Nikil D. Dutt. TC, 67(12):1818-1834, 2018. [doi]

2017

HeteroSim: A Heterogeneous CPU-FPGA SimulatorLiang Feng, Hao Liang, Sharad Sinha, Wei Zhang 0012. cal, 16(1):38-41, 2017. [doi]

PAAS: A system level simulator for heterogeneous computing architecturesTingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang 0012. fpl 2017: 1-8 [doi]

Decision tree based hardware power monitoring for run time dynamic power management in FPGAZhe Lin, Wei Zhang 0012, Sharad Sinha. fpl 2017: 1-8 [doi]

A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptographyTao Luo, Bingsheng He, Wei Zhang 0012, Douglas L. Maskell. iccad 2017: 276-282 [doi]

Pipeline Reconfigurable DSP for Dynamically Reconfigurable ArchitecturesRakesh Warrier, Wei Zhang 0012, Chan Hua Vun. cssp, 36(9):3799-3824, 2017. [doi]

Fracturable DSP Block for Multi-context Reconfigurable ArchitecturesRakesh Warrier, Shanker Shreejith, Wei Zhang 0012, Chan Hua Vun, Suhaib A. Fahmy. cssp, 36(7):3020-3033, 2017. [doi]

2014

A low-power pipelined MAC architecture using Baugh-Wooley based multiplierRakesh Warrier, Chan Hua Vun, Wei Zhang 0012. gcce 2014: 505-506 [doi]

2013

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memoriesXuan Wang, Jiang Xu, Wei Zhang 0012, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang. date 2013: 1221-1224 [doi]

Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-ChipYiyuan Xie, Mahdi Nikdast, Jiang Xu, Xiaowen Wu, Wei Zhang 0012, Yaoyao Ye, Xuan Wang, Zhehui Wang, Weichen Liu. tvlsi, 21(10):1823-1836, 2013. [doi]

NBTI-aware circuit node criticality computationShengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang 0012, Pallav Gupta, Yu Cao. jetc, 9(3):23, 2013. [doi]

System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-ChipYaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang 0012, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu. tvlsi, 21(2):292-305, 2013. [doi]

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-ChipYaoyao Ye, Jiang Xu, Baihan Huang, Xiaowen Wu, Wei Zhang 0012, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, Zhe Wang. tcad, 32(4):584-596, 2013. [doi]

2012

2011

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interfaceWei Zhang 0012, Jiale Huang, Shengqi Yang, Pallav Gupta. date 2011: 1071-1076 [doi]

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC ModelsWeichen Liu, Jiang Xu, Jogesh K. Muppala, Wei Zhang 0012, Xiaowen Wu, Yaoyao Ye. esl, 3(1):46-49, 2011. [doi]

2010

UNION: A unified inter/intra-chip optical network for chip multiprocessorsXiaowen Wu, Yaoyao Ye, Wei Zhang 0012, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu. NANOARCH 2010: 35-40 [doi]

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