Abstract is missing.
- Code Selection for Media Processors with SIMD InstructionsRainer Leupers. 4-8 [doi]
- Analysis of High-Level Address Code Transformations for Programmable ProcessorsSumit Gupta, Rajesh K. Gupta, Miguel Miranda, Francky Catthoor. 9-13 [doi]
- Free MDD-Based Software Optimization Techniques for Embedded SystemsChunghee Kim, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli. 14 [doi]
- Quantitative Comparison of Power Management AlgorithmsYung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini. 20-26 [doi]
- Efficient Power Co-Estimation Techniques for System-on-Chip DesignMarcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno. 27-34 [doi]
- A Discrete-Time Battery Model for High-Level Power EstimationLuca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 35 [doi]
- The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog CircuitsRobert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich. 42-47 [doi]
- A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated CircuitsOscar Guerra, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez. 48-52 [doi]
- Layout-Oriented Synthesis of High Performance Analog CircuitsMohamed Dessouky, Marie-Minerve Louërat, Jacky Porte. 53-57 [doi]
- Technology Mapping and Retargeting for Field-Programmable Analog ArraysSree Ganesan, Ranga Vemuri. 58 [doi]
- Tutorial StatementYervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf. 66 [doi]
- The Road to Better Reliability and Yield Embedded DfM ToolsKees Veelenturf. 67 [doi]
- Yield Improvement and Repair Trade-Off for Large Embedded MemoriesYervant Zorian. 69-70 [doi]
- Stay Away from Minimum Design-Rule ValuesChris W. H. Strolenberg. 71 [doi]
- System Level Design Using C++Diederik Verkest, Joachim Kunkel, Frank Schirrmeister. 74 [doi]
- Techniques for Reducing Read Latency of Core Bus WrappersRoman L. Lysecky, Frank Vahid, Tony Givargis. 84-91 [doi]
- Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated ApplicationsFrederik Vermeulen, Francky Catthoor, Hugo De Man, Diederik Verkest. 92-98 [doi]
- Virtual Fault Simulation of Distributed IP-Based DesignsMarcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli. 99 [doi]
- Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence ComputationXiaoping Tang, D. F. Wong, Ruiqi Tian. 106-111 [doi]
- A New Effective And Efficient Multi-Level Partitioning AlgorithmYoussef Saab. 112-116 [doi]
- Faster Optimal Single-Row Placement with Fixed OrderingUlrich Brenner, Jens Vygen. 117-121 [doi]
- Layout Compaction for Yield Optimization via Critical Area MinimizationYoucef Bourai, C.-J. Richard Shi. 122 [doi]
- Test Synthesis for Mixed-Signal SOC PathsSule Ozev, Ismet Bayraktaroglu, Alex Orailoglu. 128-133 [doi]
- Analysis and Minimization of Test Time in a Combined BIST and External Test ApproachMakoto Sugihara, Hiroto Yasuura, Hiroshi Date. 134-140 [doi]
- CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a ChipMounir Benabdenbi, Walid Maroufi, Meryem Marzouki. 141-145 [doi]
- Design and Test Space Exploration of Transport-Triggered ArchitecturesV. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff. 146 [doi]
- Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and VectorsAxel Jantsch, Per Bjuréus. 154-160 [doi]
- MASCOT: A Specification and Cosimulation Method Integrating Data and Control FlowPer Bjuréus, Axel Jantsch. 161-168 [doi]
- Delay-Insensitive Interface Specification and SynthesisMark B. Josephs, Dennis P. Furey. 169 [doi]
- A 50 Mbit/s Iterative Turbo-DecoderF. Viglione, Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni. 176-180 [doi]
- Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband ProcessingU. Girola, A. Picciriello, D. Vincenzoni. 181-185 [doi]
- Protocol Stack-Based Telecom-EmulatorTakahiro Murooka, Toshiaki Miyazaki. 186 [doi]
- Transformational Placement and SynthesisWilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty. 194-201 [doi]
- Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAsBalakrishna Kumthekar, Fabio Somenzi. 202-207 [doi]
- Constructive Library-Aware Synthesis Using SymmetriesVictor N. Kravets, Karem A. Sakallah. 208 [doi]
- A BIST Scheme for On-Chip ADC and DAC TestingJiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng. 216-220 [doi]
- An on Chip ADC Test StructureYun-Che Wen, Kuen-Jong Lee. 221-225 [doi]
- Reuse of Existing Resources for Analog BIST of a Switch Capacitor FilteÉrika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski. 226 [doi]
- A BDD-Based Satisfiability Infrastructure Using the Unate Recursive ParadigmPriyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang. 232-236 [doi]
- Automatic Lighthouse Generation for Directed State Space SearchPraveen Yalagandula, Adnan Aziz, Vigyan Singhal. 237-242 [doi]
- Analyzing Real-Time SystemsJürgen Ruf, Thomas Kropf. 243 [doi]
- A Generic Architecture for On-Chip Packet-Switched InterconnectionsPierre Guerrier, Alain Greiner. 250-256 [doi]
- Memory Arbitration and Cache Management in Stream-Based SystemsFrançoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen. 257-262 [doi]
- HW/SW Codesign of an Engine Management SystemMassimo Baleani, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Claudio Turchetti. 263 [doi]
- Wave Steered FSMsLuca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska. 270-276 [doi]
- Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino LogicJovanka Ciric, Gin Yee, Carl Sechen. 277-282 [doi]
- Gate Sizing Using a Statistical Delay ModelE. T. A. F. Jacobs, Michel R. C. M. Berkelaar. 283 [doi]
- Optimal Hardware Pattern Generation for Functional BISTSilvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich. 292-297 [doi]
- Built-In Generation of Weighted Test Sequences for Synchronous Sequential CircuitsIrith Pomeranz, Sudhakar M. Reddy. 298-304 [doi]
- Diagnostic Testing of Embedded Memories Using BISTTimothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick. 305 [doi]
- Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from CLuc Séméria, Koichi Sato, Giovanni De Micheli. 312-319 [doi]
- An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency ImprovementSatish Ganesan, Ranga Vemuri. 320-325 [doi]
- Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based EmulationOliver Bringmann, Wolfgang Rosenstiel, Carsten Menn. 326-332 [doi]
- Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip DesignJörg Henkel, Tony Givargis, Frank Vahid. 333 [doi]
- Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery CircuitsAlper Demir, Peter Feldmann. 340-344 [doi]
- A New Approach for Computation of Timing Jitter in Phase Locked LoopsMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney. 345-349 [doi]
- Compact Modeling of Nonlinear Distortion in Analog Communication CircuitsPiet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens. 350 [doi]
- On Using Satisfiability-Based Pruning Techniques in Covering AlgorithmsVasco M. Manquinho, João P. Marques Silva. 356-363 [doi]
- An Efficient Heuristic Approach to Solve the Unate Covering ProblemRoberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo. 364-371 [doi]
- On the Generation of Multiplexer Circuits for Pass Transistor LogicChristoph Scholl, Bernd Becker. 372 [doi]
- On Applying Incremental Satisfiability to Delay Fault TestingJoonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva. 380-384 [doi]
- Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial ExperienceFulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti. 385-389 [doi]
- A VHDL Error Simulator for Functional Test GenerationAlessandro Fin, Franco Fummi. 390-395 [doi]
- Functional Test Generation for Full Scan CircuitsIrith Pomeranz, Sudhakar M. Reddy. 396 [doi]
- Shared Memory Implementations of Synchronous Dataflow SpecificationsPraveen K. Murthy, Shuvra S. Bhattacharyya. 404-410 [doi]
- Constraint-Driven System PartitioningMarisa Luisa López-Vallejo, Jesús Grajal, Juan Carlos López. 411-416 [doi]
- A System-Level Synthesis Algorithm with Guaranteed Solution QualityU. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary. 417 [doi]
- How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis. 426 [doi]
- Meeting Delay Constraints in DSM by Minimal Repeater InsertionI-Min Liu, Adnan Aziz, D. F. Wong. 436-440 [doi]
- A Bus Delay Reduction Technique Considering CrosstalkKei Hirose, Hiroto Yasuura. 441-445 [doi]
- Single Step Current Driven Routing of Multiterminal Signal Nets for Analog ApplicationsThorsten Adler, Erich Barke. 446-450 [doi]
- Static Timing Analysis Taking Crosstalk into AccountMatthias Ringe, Thomas Lindenkreuz, Erich Barke. 451 [doi]
- A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay DefectsSungju Park, Taehyung Kim. 458 [doi]
- Alternative Test Methods Using IEEE 1149.4Uros Kac, Franc Novak, Srecko Macek, Marina Santo Zarnik. 463-467 [doi]
- Test Quality and Fault Risk in Digital Filter Datapath BISTLaurence Goodby, Alex Orailoglu. 468-475 [doi]
- A Fault Simulation Methodology for MEMSRichard Rosing. 476-457 [doi]
- Abstraction from Counters: An Application on Real-Time SystemsGeorge Logothetis, Klaus Schneider. 486-493 [doi]
- Automatic Abstraction for Worst-Case Analysis of Discrete SystemsFelice Balarin. 494-501 [doi]
- Iterative Abstraction-Based CTL Model CheckingJae-Young Jang, In-Ho Moon, Gary D. Hachtel. 502 [doi]
- A Design Automation Roadmap for Europe Panel discussionJoseph Borel, Frank Ghenassia, Jean-Jacques Bronner, Irmtraud Rugen-Herzig, Wolfgang Rosenstiel, Anton Sauer. 510 [doi]
- Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line ModelYouxin Gao, D. F. Wong. 512 [doi]
- Predicting Coupled Noise in RC CircuitsBernard N. Sheehan. 517 [doi]
- Clocktree RLC Extraction with Efficient Inductance ModelingNorman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He. 522 [doi]
- All Digital Built-in Delay and Crosstalk Measurement for On-Chip BusesChauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee. 527 [doi]
- A Vhdl-Based Methodology for Design and Verification of Pipeline A/D ConvertersEduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas. 534-538 [doi]
- Assessing the Cost Effectiveness of Integrated PassivesMichael Scheffler, Gerhard Tröster. 539-543 [doi]
- Non-Linear Components for Mixed Circuits Analog Front-EndLuigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco. 544 [doi]
- Static Timing Analysis of Embedded Software on Advanced Processor ArchitecturesAndré Hergenhan, Wolfgang Rosenstiel. 552-559 [doi]
- Efficient Resource Arbitration in Reconfigurable Computing EnvironmentsIyad Ouaiss, Ranga Vemuri. 560-566 [doi]
- Bus Access Optimization for Distributed Embedded Systems Based on Schedulability AnalysisPaul Pop, Petru Eles, Zebo Peng. 567 [doi]
- Standards for System-Level Design: Practical Reality or Solution in Search of a Question?Christopher K. Lennard, Patrick Schaumont, Gjalt G. de Jong, Anssi Haverinen, Pete Hardee. 576 [doi]
- Evaluating System Dependability in a Co-Design FrameworkMarcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno. 586-590 [doi]
- Cost Reduction and Evaluation of a Temporary Faults Detecting TechniqueLorena Anghel, Michael Nicolaidis. 591-598 [doi]
- Detection of Defective Sensor Elements Using Sigma-Delta-Modulation and a Matched FilterD. Weiler, O. Machul, D. Hammerschmidt, Bedrich J. Hosticka. 599 [doi]
- System Level Online Power Management AlgorithmsDinesh Ramanathan, Rajesh K. Gupta. 606-605 [doi]
- Architectural Power Optimization by Bus SplittingCheng-Ta Hsieh, Massoud Pedram. 612-611 [doi]
- A Power Reduction Technique with Object Code Merging for Application Specific Embedded ProcessorsTohru Ishihara, Hiroto Yasuura. 617-616 [doi]
- Automating RT-Level Operand Isolation to Minimize Power Consumption in DatapathsMichael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch. 624 [doi]
- The Future of Flexible HW Platform Architectures Panel DiscussionRolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers. 634 [doi]
- Designing Closer to the EdgeSani R. Nassif. 636 [doi]
- Reducing the Complexity of Defect Level Modeling Using the Clustering EffectJosé T. de Sousa, Vishwani D. Agrawal. 640-644 [doi]
- Influence of Manufacturing Variations in IDDQ Measurements: A New Test CriterionJuan M. Díez, Juan Carlos López. 645-649 [doi]
- Parametric Fault Simulation and Test Vector GenerationKhaled Saab, Naim Ben Hamida, Bozena Kaminska. 650 [doi]
- Parallel and Distributed VHDL SimulationDragos Lungeanu, C.-J. Richard Shi. 658-662 [doi]
- Fast Hardware-Software Coverification by Optimistic Execution of Real ProcessorSungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi. 663-668 [doi]
- Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description LanguageStefan Pees, Andreas Hoffmann, Heinrich Meyr. 669-673 [doi]
- Logic Simulation Using Networks of State MachinesPeter M. Maurer. 674-678 [doi]
- A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor LevelNorbert Fröhlich, Volker Gloeckel, Josef Fleischmann. 679 [doi]
- From High-Level Specifications Down to Software Implementations of Parallel Embedded Real-Time SystemsCarsten Rust, Friedhelm Stappert, Peter Altenbernd, Jürgen Tacken. 686-691 [doi]
- An Object Oriented Design Method for Reconfigurable Computing SystemsMartyn Edwards, Peter Green. 692-696 [doi]
- System Synthesis for Multiprocessor Embedded ApplicationsLuigi Carro, Márcio Eduardo Kreutz, Flávio Rech Wagner, Márcio Oyamada. 697-702 [doi]
- System Design Based on Single Language and Single-Chip Java ASIP MicrocontrollerSérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi. 703 [doi]
- Cost and Benefit Models for Logic and Memory BISTJuin-Ming Lu, Cheng-Wen Wu. 710-714 [doi]
- Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential CircuitsNicola Nicolici, Bashir M. Al-Hashimi. 715-722 [doi]
- Detecting Undetectable Controller Faults Using Power AnalysisJoan Carletta, Christos A. Papachristou, Mehrdad Nourani. 723-728 [doi]
- Multi-Node Static Logic Implications for Redundancy IdentificationKabir Gulrajani, Michael S. Hsiao. 729 [doi]
- Dynamic Power Management of Laptop Hard DiskTajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli. 736 [doi]
- Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource ConstraintsLars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel. 737 [doi]
- Area Optimization of Analog Circuits Considering Matching ConstraintsChristian Paulus, Ulrich Kleine, Roland Thewes. 738 [doi]
- XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing ToolF. M. Pérez-Montes, F. Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández, Ángel Rodríguez-Vázquez. 739 [doi]
- Evaluation of Interconnects with TDRUlf Pillkahn. 740 [doi]
- Structural Testing on Real BoardsPeter Bach, Michael Bosch. 741 [doi]
- Cycle-True Simulation of the ST10 MicrocontrollerLovic Gauthier, Ahmed Amine Jerraya. 742 [doi]
- Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision DiagramsAdam Morawiec, Raimund Ubar, Jaan Raik. 743 [doi]
- Mixed-Signal BIST Using Correlation and Reconfigurable HardwareJosé Machado da Silva, J. Soeiro Duarte, José Silva Matos. 744 [doi]
- An Experimental Study of Satisfiability Search HeuristicsKarem A. Sakallah, Fadi A. Aloul, João P. Marques Silva. 745 [doi]
- A Memory Architecture with 4-Address Configurations for Video Signal ProcessingSunho Chang, Jong-Sun Kim, Lee-Sup Kim. 746 [doi]
- A Hardware Platform for VLIW Based Emulation of Digital DesignsGunter Haug, Udo Kebschull, Wolfgang Rosenstiel. 747 [doi]
- Architecture Exploration of Parameterizable EPIC SOC ArchitecturesAshok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau. 748 [doi]
- Improving the Schedule Quality of Static-List Time-Constrained SchedulingSriram Govindarajan, Ranga Vemuri. 749 [doi]
- Synthesis for Mixed CMOS/PTl LogicCongguang Yang, Maciej J. Ciesielski. 750 [doi]
- TOP: An Algorithm for Three-Level Optimization of PLDsElena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio. 751 [doi]
- Testing Arithmetic Coprocessor in System EnvironmentJanusz Sosnowski, Tomasz Bech. 752 [doi]
- A Flexible Specification Framework for Hardware-Software CodesignJosé Manuel Moya, Francisco Moya, Juan Carlos López, Santiago Domínguez. 753 [doi]
- An Integrated Design Environment for Early Stage Conceptual DesignJingyan Zuo, Stephen W. Director. 754 [doi]
- A Web-Based System for Assessing and Searching for DesignsHilary J. Kahn, Andy Carpenter, Nigel A. Whitaker. 755 [doi]
- A Versatile Built-In Self-Test Scheme for Delay Fault TestingY. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos. 756 [doi]
- Effective Low Power BIST for DatapathsDimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian. 757 [doi]
- Exploiting Hierarchy for Multiple Error Correction in Combinational CircuitsDirk W. Hoffmann, Thomas Kropf. 758 [doi]
- Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer LevelJens Schönherr, Bernd Straube. 759 [doi]
- A Single Phase Latch for High Speed GaAs Domino CircuitsSaeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, J. Sosa. 760 [doi]
- An Incremental Specification Flow for Real Time Embedded SystemsAlex Niemegeers, Gjalt G. de Jong. 761 [doi]
- Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under CheckValery A. Vardanian, Liana B. Mirzoyan. 762 [doi]
- On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage ValuesCecilia Metra, Michele Favalli, Bruno Riccò. 763 [doi]
- Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICsCarsten Wegener, Michael Peter Kennedy. 765 [doi]