Abstract is missing.
- K*BMDs: A New Data Structure for VerificationRolf Drechsler, Bernd Becker, Stefan Ruppertz. 2-8 [doi]
- Exploiting Functional Dependencies in Finite State Machine VerificationC. A. J. van Eijk, Jochen A. G. Jess. 9-14 [doi]
- An Efficient Algorithm for Real-Time Symbolic Model CheckingJürgen Frößl, Thomas Kropf, Joachim Gerlach. 15-21 [doi]
- The Use of Microelectronics for Future Telecom and Multimedia SystemsJacques Wenin, Geert van Wauwe, Mark Genoe, Danny Sallaerts. 22 [doi]
- System design tools for broadband telecom network applicationsBill Lin. 23-26 [doi]
- Design challenges of high speed ATM communication ASICsJ. L. Conesa. 27-29 [doi]
- Deterministic Pattern Generation for Weighted Random Pattern TestingBirgit Reeb, Hans-Joachim Wunderlich. 30-36 [doi]
- Deterministic Test Pattern Reproduction by a CounterDimitrios Kagaris, Spyros Tragoudas, Amitava Majumdar. 37-41 [doi]
- Multiplicative Window Generators of Pseudo-random Test VectorsJanusz Rajski, Jerzy Tyszer. 42-49 [doi]
- High-level synthesis of gracefully degradable ASICsWah Chan, Alex Orailoglu. 50-54 [doi]
- High-Level Synthesis of Recoverable MicroarchitecturesSeong Yong Ohm, Douglas M. Blough, Fadi J. Kurdahi. 55-62 [doi]
- Reducing Address Bus Transitions for Low Power Memory MappingPreeti Ranjan Panda, Nikil D. Dutt. 63-71 [doi]
- Assessing the Quality Level of Digital CMOS IC's under the Hypothesis of Non-Uniform Distribution of Fault ProbabilitiesFrancesco Corsi, Cristoforo Marzocca, S. Martino. 72-78 [doi]
- DFSIM: A Gate-Delay Fault Simulator for Sequential CircuitsP. Cavallera, Patrick Girard, Christian Landrault, Serge Pravossoudovitch. 79-87 [doi]
- Surprises in Sequential Redundancy IdentificationMahesh A. Iyer, David E. Long, Miron Abramovici. 88-95 [doi]
- Optimal Code Placement of Embedded Software for Instruction CachesHiroyuki Tomiyama, Hiroto Yasuura. 96-101 [doi]
- A Graph Based Processor Model for Retargetable Code GenerationJohan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man. 102-107 [doi]
- Operation Serializability for Embedded SystemsRajesh K. Gupta. 108-115 [doi]
- IDDQ: you heard the hype, but what's really coming?Keith Baker. 116-119 [doi]
- Decentralized BIST for 1149.1 and 1149.5 Based InterconnectsChauchin Su, Shyh-Jye Jou, Yuan-Tzu Ting. 120-125 [doi]
- Test Structures on MCM Active Substrate: Is it worthwhile?Joan Oliver, Hans G. Kerkhoff. 126-130 [doi]
- Relay Propagation Scheme for Testing of MCMs on Large Area SubstratesKoppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian. 131-137 [doi]
- A Specification Invariant Technique for Regularity Improvement between Flow-Graph ClustersMartin Janssen, Francky Catthoor, Hugo De Man. 138-143 [doi]
- An evolution programming approach on multiple behaviors for the design of application specific programmable processorsWei Zhao, Christos A. Papachristou. 144-150 [doi]
- Area and Timing Estimation for Lookup Table Based FPGAsMin Xu, Fadi J. Kurdahi. 151-159 [doi]
- Detailed-Routability of FPGAs with Extremal Switch-Block StructuresYasuhiro Takashima, Atsushi Takahashi 0001, Yoji Kajitani. 160-164 [doi]
- Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAsAnmol Mathur, C. L. Liu. 165-169 [doi]
- A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAsSrilata Raman, C. L. Liu, Larry G. Jones. 170-175 [doi]
- Built-in self test architectures for multistage interconnection networksErnst G. Bernard, Sven Simon, Josef A. Nossek. 176-180 [doi]
- Designing Self-Testable Multi-Chip ModulesYervant Zorian, Hakim Bederr. 181-185 [doi]
- Achieving Fault Secureness in Parity Prediction Arithmetic Operators: General Conditions and ImplementationsMichael Nicolaidis, Salvador Manich, Joan Figueras. 186-194 [doi]
- Asynchronous SRT Dividers: The Real CostHicham Boutamine, Alain Guyot, Bachar Elhassan, Marc Renaudin. 195-199 [doi]
- Error Detection in Fault Secure Controllers using State EncodingEckart Voskamp, Wolfgang Rosenstiel. 200-204 [doi]
- Power Optimization of Delay Constrained CMOS Bus DriversS. Caufape, Joan Figueras. 205-213 [doi]
- Gate Sizing: A General Purpose Optimization ApproachOlivier Coudert. 214-218 [doi]
- Optimizing CMOS Circuits for Low Power Using Transistor ReorderingEnric Musoll, Jordi Cortadella. 219-223 [doi]
- Design and selection of buffers for minimum power-delay productS. Turgis, Nadine Azémard, Daniel Auvergne. 224-229 [doi]
- An Algorithm for Zero-Skew Clock Tree Routing with Buffer InsertionY. P. Chen, D. F. Wong. 230-236 [doi]
- A Balanced-Mesh Clock Routing Technique Using Circuit PartitioningHidenori Sato, Akira Onozawa, Hiroaki Matsuda. 237-243 [doi]
- Constructing Minimal Spanning/Steiner Trees with Bounded Path LengthIksoo Pyo, Jaewon Oh, Massoud Pedram. 244-253 [doi]
- Automatic Test Generation for Maximal Diagnosis of Linear Analogue CircuitsSalvador Mir, Bernard Courtois, Marcelo Lubaszewski, Vladimir Kolarik. 254-258 [doi]
- FLAMES: A Fuzzy Logic ATMS and Model-based Expert System for Analog DiagnosisFiras Mohamed, Meryem Marzouki, Mohamed Hedi Touati. 259-263 [doi]
- Evaluation of iDD/vOUT Cross-Correlation for Mixed Current/Voltage Testing of Analogue and Mixed-Signal CircuitsJosé Machado da Silva, José Silva Matos. 264-269 [doi]
- Model Refinement for Hardware-Software CodesignJie Gong, Daniel D. Gajski, Smita Bakshi. 270-274 [doi]
- Design of an Optimal Loosely Coupled Heterogeneous Multiprocessor SystemArmin Bender. 275-281 [doi]
- Thread-based software synthesis for embedded system designYoungsoo Shin, Kiyoung Choi. 282-287 [doi]
- An Efficient Algorithm for Signal Flow Determination in Digital CMOS VLSIA. R. Baba-Ali, A. Farah. 288-293 [doi]
- Bounding Switching Activity in CMOS Circuits Using Constraint ResolutionJindrich Zejda, Eduard Cerny, S. Shenoy, Nicholas C. Rumin. 294-301 [doi]
- An Approach for a Dynamic Generation/Validation System for the Functional Simulation Considering Timing ConstraintsUlrich Heinkel, Wolfram Glauert. 302-309 [doi]
- VLSI Architecture for Motion Estimation using the Block-Matching AlgorithmCésar Sanz, Matías J. Garrido, Juan M. Meneses. 310-314 [doi]
- High Rate Soft Output Viterbi DecoderEric Luthi, Emmanuel Casseau. 315-319 [doi]
- A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip SetMitsuo Ikeda, Tsuneo Okubo, Tetsuya Abe, Yoshinori Ito, Yutaka Tashiro, Ryota Kasai. 320-327 [doi]
- Constructive Analysis of Cyclic CircuitsThomas R. Shiple, Gérard Berry, Hervé J. Touati. 328-333 [doi]
- Sequential Permissible Functions and their Application to Circuit OptimizationChih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee. 334-339 [doi]
- Structural Methods for the Synthesis of Speed-Independent CircuitsEnric Pastor, Oriol Roig, Jordi Cortadella, Alex Kondratyev. 340-349 [doi]
- Observable Time Windows: Verifying the Results of High-Level SynthesisReinaldo A. Bergamaschi, Salil Raje. 350-356 [doi]
- PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit ExtractorFrank Scherber, Erich Barke, Wolfgang Meier. 357-361 [doi]
- Including Higher-Order Moments of RC Interconnections in Layout-to-Circuit ExtractionP. J. H. Elias, N. P. van der Meijs. 362-367 [doi]
- Alternating Strategies for Sequential Circuit ATPGMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. 368-374 [doi]
- Advanced Techniques for GA-based sequential ATPGsFulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, R. Mosca. 375-379 [doi]
- On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification ProblemIrith Pomeranz, Sudhakar M. Reddy. 380-387 [doi]
- A Novel Analog Module Generator EnvironmentMarkus Wolf, Ulrich Kleine, Bedrich J. Hosticka. 388-392 [doi]
- XPRESS: A Cell Layout Generator with Integrated Transistor FoldingAvaneendra Gupta, Siang-Chun The, John P. Hayes. 393-401 [doi]
- Perturb and Simplify: Optimizing Combinational Circuits with External Don't CaresShih-Chieh Chang, Malgorzata Marek-Sadowska. 402-406 [doi]
- Rapid Gate Matching with Don't CaresA.-M. Trullemans, Q. Zhang. 407-411 [doi]
- An Implicit Algorithm for Support Minimization during Functional DecompositionChristian Legl, Bernd Wurth, Klaus Eckl. 412-419 [doi]
- Towards a Uniform Notation for Memory TestsAd J. Van de Goor, Aad Offerman, Ivo Schanstra. 420-427 [doi]
- Test and Testability Techniques for Open Defects in RAM Address DecodersManoj Sachdev. 428-434 [doi]
- RAM Testing Algorithm for Detection Linked Coupling FaultsV. G. Mikitjuk, V. N. Yarmolik, A. J. van de Goor. 435-441 [doi]
- High level CAD melds microsystems with foundriesJean-Michel Karam, Bernard Courtois, M. Bauge. 442-447 [doi]
- A conceptual design environment for micromechanismsT. Kiriyama, N. Nakajima, S. Yoshimura, S. Burgess, D. Moore, N. Shibaike. 448-453 [doi]
- SUZANA: A 3D CAD Tool for Anisotropically Etched Silicon MicrostructuresS. Büttgenbach, O. Than. 454-459 [doi]
- Recursive Bipartitioning of Signal Flow Graphs for Programmable Video Signal ProcessorsEmile H. L. Aarts, Gerben Essink, Erwin A. de Kock. 460-466 [doi]
- An Automatic Hardware-Software Partitioner Based on the Possibilistic ProgrammingIreneusz Karkowski, Ralph H. J. M. Otten. 467-472 [doi]
- Hardware/Software Partitioning using Integer ProgrammingRalf Niemann, Peter Marwedel. 473-480 [doi]
- Partial Scan High-Level SynthesisVictor Fernández, Pablo Sánchez. 481-485 [doi]
- Resynthesis of Combinational Circuts for Path Count Reduction and for Path Delay Fault TestabilityAngela Krstic, Kwang-Ting Cheng. 486-490 [doi]
- A Fast Optimal Robust Path Delay Fault Testable AdderBernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy. 491-499 [doi]
- A Memory-based Architecture for MPEG2 System Protocol LSIsMinoru Inamori, Jiro Naganuma, Haruo Wakabayashi, Makoto Endo. 500-507 [doi]
- Incorporating Multi-Chip Module Packaging Constraints into System DesignVivek Garg, Steve Lacy, David E. Schimmel, Darrell Stogner, Craig Ulmer, D. Scott Wills, Sudhakar Yalamanchili. 508-513 [doi]
- FORM: A Frame-Oriented Representation Method for Digital Telecommunication System DesignKazuhiro Shirakawa, Kazushige Higuchi, Toshiaki Miyazaki, Kazuhiro Hayashi, Kazuhisa Yamada. 514-521 [doi]
- Defect-Oriented Experiments in Fault Modelling and Fault Simulation of Microsystem ComponentsWolfgang Vermeiren, Bernd Straube, Andreas Holubek. 522-527 [doi]
- Applied design and analysis of microsystemsJean-Michel Karam, Bernard Courtois, András Poppe, Klaus Hofmann, Márta Rencz, Manfred Glesner, Vladimir Székely. 528-532 [doi]
- Step by Step from Specification to Realization of an Electrochemical MicrosystemWolfgang Süß, K. Lindemann, Horst Eggert, Martina Gorges-Schleuter, Wilfried Jakob, W. Hoffmann, Reinhard Rapp. 533-541 [doi]
- Exploit Analog IFA to Improve Specification Based TestsBert Atzema, Taco Zwemstra. 542-546 [doi]
- Analogue Fault Modelling and Simulation for Supply Current MonitoringMark Zwolinski, Chris D. Chalk, Brian R. Wilkins. 547-552 [doi]
- Approaches to On-chip Testing of Mixed Signal Macros in ASICsR. A. Cobley. 553-559 [doi]
- Fast Computation of Substrate Resistances in Large CircuitsArjan J. van Genderen, N. P. van der Meijs, T. Smedes. 560-565 [doi]
- ETS-A: A New Electrothermal Simulator for CMOS VLSI CircuitsYi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang. 566-570 [doi]
- Simulated Annealing Algorithm with Multi-Molecule: An Approach to Analog SynthesisH. Z. Yang, C. Z. Fan, H. Wang, R. S. Liu. 571-577 [doi]
- Iddq Testing for High Performance CMOS - The Next Ten YearsThomas W. Williams, Rohit Kapur, M. Ray Mercer, Robert H. Dennard, Wojciech Maly. 578-583 [doi]
- Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based DesignM. Rullán, C. Ferrer, J. Oliver, Diego Mateo, Antonio Rubio. 584-588 [doi]
- Design for Testability of Gated-Clock FSMsMichele Favalli, Luca Benini, Giovanni De Micheli. 589-597 [doi]
- VLSI Design of a High Speed Soft Decision Viterbi DetectorTom Conway, John Nelson. 598 [doi]
- A Hardware/Software Codesign Case Study: Design of a Robot Arm ControllerMohamed Abid, Adel Changuel, Ahmed Amine Jerraya. 599 [doi]
- A Technique for Avoiding Isomorphic Netlists in Architectural SynthesisPeter Marwedel, Steven Bashford, Rainer Dömer, Birger Landwehr, Ingolf Markhof. 600 [doi]
- Algebraic Support for Transformational Hardware AllocationJosé M. Mendías, Román Hermida, Milagros Fernández. 601 [doi]
- A spectral method for Boolean function matchingD. M. Miller. 602 [doi]
- FPGA synthesis for minimum area, delay and powerKuo-Rueih Ricky Pan, Massoud Pedram. 603 [doi]
- An Efficient Method for the Self-Consistent Electro-Thermal Simulation and its Integration into a CAD FrameworkVladimir Székely, András Poppe, Márta Rencz, Gabor Farkas, Alpar Csendes, Andras Pahi. 604 [doi]
- A System for Modelling and Proving CircuitsMichel Allemand, Solange Coupet-Grimal, Line Jakubiec, Jean-Luc Paillet. 605 [doi]
- Exploiting Partitioned Transition Relations for Efficient Symbolic Model Checking in CTLAles Casar, Zmago Brezocnik, Tatjana Kapus. 606 [doi]
- Formal Specification of a Reactive System: An Exercise in VHDL, LOTOS and UNITYLaurence Pierre. 607 [doi]
- Generalized Recognition of Gates: A VLSI Abstraction ToolJean Bruce Guignet. 608 [doi]
- A Combined Pairing and Chaining Algorithm for CMOS Layout GenerationA. Josep Velasco, Xavier Marin, Jordi Carrabina, Rafael Peset Llopis. 609 [doi]
- Self-Checking and Fault Tolerant Approaches Can Help BIST Fault Coverage: A Case StudyFulvio Corno, Paolo Prinetto, Matteo Sonza Reorda. 610 [doi]
- Hardware Check of Arithmetic Devices with Abridged Execution of OperationsAlexander V. Drozd, Wael Hassonah, Michel Lobachov. 611 [doi]
- Realistic Fault Extraction for BoardsJosé T. de Sousa, T. Shen, Peter Y. K. Cheung. 612 [doi]
- Applying Behavioural Level Test Generation to High-Level Design ValidationMatthias Gulbins, Bernd Straube. 613 [doi]
- Design of Test Modules for the Analysis of MCM InterconnectsClaudio Truzzi, Eric Beyne, Edwin Ringoot. 614 [doi]
- Economics Modelling and Optimisation of MCM Test StrategiesChryssa Dislis, Ian P. Jalowiecki. 615 [doi]
- System Fault Diagnosis based on a Fuzzy Qualitative ApproachMohamed Hedi Touati, Firas Mohamed, Meryem Marzouki. 616 [doi]
- An Automated Design Environment for Micromechanical SensorsA. Murthi, F. Rocaries. 617 [doi]
- Methods and Tools for the Design of Electrostatic MicromotorsT. Johansson, K. Hameyer, R. Belmans. 618 [doi]
- Design Kit for Microsystems Design for an Enhanced CMOS ProcessJordi Carrabina, L. Hébrard, A. Merlos, Joaquín Saiz, J. Bausells. 619 [doi]