Abstract is missing.
- PASTA: Partial Scan to Enhance Test CompactionIrith Pomeranz, Sudhakar M. Reddy. 4-7 [doi]
- On Applying Set Covering Models to Test Set CompactionPaulo F. Flores, Horácio C. Neto, João P. Marques Silva. 8-11 [doi]
- On Test Generation with A Limited Number of TestsHideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara. 12-15 [doi]
- Functional ATPG for Delay FaultsSpyros Tragoudas, Maria K. Michael. 16-19 [doi]
- On Path Delay Fault Testing of Multiplexer - Based ShiftersHaridimos T. Vergos, Dimitris Nikolos, Y. Tsiatouhas, Th. Haniotakis, Michael Nicolaidis. 20-23 [doi]
- A Test Vector Ordering Technique for Switching Activity Reduction During Test OperationPatrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch. 24 [doi]
- VLSI Implementation of Early Branch Prediction Circuits for High Performance ComputingAamir A. Farooqui, Vojin G. Oklobdzija. 30-33 [doi]
- The Design of a Register Renaming UnitBenjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin. 34-37 [doi]
- Efficient and Safe Asynchronous Wave-Pipeline Architectures for Datapath and Control Unit ApplicationsO. Hauck, M. Garg, Sorin A. Huss. 38-41 [doi]
- Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAMJörg Hilgenstock, Klaus Herrmann, Peter Pirsch. 42-45 [doi]
- Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and CorrelationJanardhan H. Satyanarayana, Keshab K. Parhi. 46-49 [doi]
- Adaptive Hard Disk Power Management on Personal ComputersYung-Hsiang Lu, Giovanni De Micheli. 50 [doi]
- Inductance Effects in RLC TreesYehea I. Ismail, Eby G. Friedman, José Luis Neves. 56-59 [doi]
- S2P: A Stable 2-Pole RC Delay and Coupling Noise MetricEmrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi. 60-63 [doi]
- ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design EnvironmentYanhong Yuan, Prithviraj Banerjee. 64-67 [doi]
- An Exact Analytical Time-Domain Model Of Distributed RC Interconnects for High Speed Nonlinear Circuit ApplicationsNinglong Lu, Ibrahim N. Hajj. 68 [doi]
- A Radix-16 SRT Division Unit with Speculation of the Quotient DigitsGianluca Cornetta, Jordi Cortadella. 74-77 [doi]
- Area-Efficient Area Pad Design for High Pin-Count ChipsLouis Luh, John Choma Jr., Jeffrey T. Draper. 78-81 [doi]
- New 2 Gbit/s CMOS I/O padsGuido Masera, Gianluca Piccinini, Massimo Ruo Roth, Maurizio Zamboni. 82-85 [doi]
- A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software PartitioningJörg Henkel. 86 [doi]
- On Optimizing Test Strategies for Analog CellsAnna Maria Brosa, Joan Figueras. 92-96 [doi]
- Novel Design for Testability of a Mixed-Signal VLSI ICErik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang. 97-100 [doi]
- The Development of Analog SPICE Behavioral Model Based on IBIS ModelYing Wang, Han Ngee Tan. 101 [doi]
- Fault Coverage Estimation for Early Stage of VLSI DesignVon-Kyoung Kim, Tom Chen, Mick Tegethoff. 105-108 [doi]
- Pseudo-Exhaustive Testing of Sequential CircuitsBassam Shaer, Sami A. Al-Arian, David L. Landis. 109 [doi]
- Self-Assembly Based Approaches for Metal/Molecule/Semiconductor Nanoelectronic CircuitsDavid B. Janes, R. P. Andres, E. H. Chen, J. Dicke, V. R. Kolagunta, J. Lauterbach, T. Lee, J. Liu, M. R. Melloch, E. L. Peckham, T. Pletcher, R. Reifenberger, H. J. Ueng, B. L. Walsh, J. M. Woodall, C. P. Kubiak, B. Kasibhatla. 114-117 [doi]
- Logic in Wire: Using Quantum Dots to Implement a MicroprocessorMichael T. Niemier, Peter M. Kogge. 118-121 [doi]
- Why is Time-Varying Control Necessary for Signal Processing with Locally-Connected Quantum-Dot Arrays?Árpád Csurgay, Craig S. Lent, Wolfgang Porod. 122 [doi]
- Resonant Tunneling Technology for Mixed Signal and Digital Circuits in the 10-100 GHz DomainT. P. E. Broekaert, B. Brar, F. Morris, A. C. Seabaugh, G. Frazier. 123 [doi]
- Efficient Algorithms for Finding Highly Acceptable Designs Based on Module-Utility SelectionsChantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Sharon Hu. 128-131 [doi]
- Reducing BDD Size by Exploiting Structural ConnectivityRonnie L. Wright, Michael A. Shanblatt. 132-135 [doi]
- An Integrated Approach for Synthesizing LUT NetworksShigeru Yamashita, Hiroshi Sawada, Akira Nagoya. 136-139 [doi]
- Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested LoopsAbhijit Ghosh, Sandeep K. Lodha, Ranga Vemuri. 140-143 [doi]
- Design Issues in Synthesis of Reusable CoresRohit Sharma, C. P. Ravikumar. 144 [doi]
- Ultrahigh-Speed Circuits Using Resonant Tunneling DevicesMasafumi Yamamoto, Hideaki Matsuzaki, Toshihiro Itoh, Takao Waho, T. Akeyoshi, J. Osaka. 150-153 [doi]
- A Novel High-Speed Flip-Flop Circuit Using RTDs and HEMTsHideaki Matsuzaki, Toshihiro Itoh, Masafumi Yamamoto. 154-157 [doi]
- Design and Analysis of a Novel Quantum-MOS Sense Amplifier CircuitTetsuya Uemura, Pinaki Mazumder. 158-161 [doi]
- Integration of InAs/AlSb/GaSb Resonant Interband Tunneling Diodes with Heterostructure Field-Effect Transistors for Ultra-High-Speed Digital Circuit ApplicationsPatrick Fay, Gary H. Bernstein, David H. Chow, J. Schulman, Pinaki Mazumder, W. Williamson, B. K. Gilbert. 162-165 [doi]
- A Memory Design in QCAs using the SQUARES FormalismDaniel Berzon, Terry J. Fountain. 166 [doi]
- Transistor Level Synthesis for Static CMOS Combinational CircuitsChia-Pin R. Liu, Jacob A. Abraham. 172-175 [doi]
- SINMEF - A Decomposition Based Synthesis Tool for Large FSMsCarlos Humberto Llanos Quintero, Marius Strum. 176-179 [doi]
- An Approach for Testing Safety-Critical SoftwareWeiwei Li, Zhongwei Xu, Yan Jin. 180-183 [doi]
- Design Recovery for Incomplete Combinational LogicTravis E. Doom, Anthony S. Wojcik, Moon-Jung Chung. 184-187 [doi]
- Regression-Based Macromodeling for Delay Estimation of Behavioral ComponentsAlberto Macii, Enrico Macii, Giuseppe Odasso, Massimo Poncino, Riccardo Scarsi. 188-191 [doi]
- Efficiently Searching the Optimal Design SpaceStephen A. Blythe, Robert A. Walker. 192 [doi]
- A Bandpass Sigma-Delta for Software Low-Power and Low-Voltage Radio by Using PATH TechniqueYiu Wu, John Ling, Ward J. Helms. 198-201 [doi]
- No-Race Charge-Recycling Differential Logic (NCDL)Seung-Moon Yoo, Sung-Mo Kang. 202-205 [doi]
- Linear Transconductors Using Low Voltage Low Power Square-Law Cmos CellsTuna B. Tarim, Mohammed Ismail. 206-209 [doi]
- Current Sensor on the Base of Permanent Pre-chargeable AmplifierVictor Varshavsky, Masayuki Tsukisaka. 210-213 [doi]
- Parallel Saturating Fractional Arithmetic UnitsNavindra Yadav, Michael J. Schulte, John Glossner. 214-217 [doi]
- Residue Arithmetic Circuits Based on Signed-Digit Number Representation and the VHDL ImplementationShugang Wei, Kensuke Shimizu. 218 [doi]
- Modell Evaluation Using Genetic Manipulation TechniquesH.-Ch. Dahmen, Uwe Gläser, Z. Stamenkovic. 224-225 [doi]
- A Genetic Algorithm for Register AllocationKhaled M. Elleithy, E. G. Abd-El-Fattah. 226-227 [doi]
- Congestion Mitigation During PlacementKanad Chakraborty, Natesan Venkateswaran. 228-229 [doi]
- A Spiffy Tool for the Simultaneous Placement and Global Routing for Three-Dimensional Field-Programmable Gate ArraysJohn Karro, James P. Cohoon. 230-231 [doi]
- Formal Verification of Tree-Structured Carry-Lookahead AddersSae Hwan Kim, Shiu-Kai Chin. 232-233 [doi]
- Bounding Algorithms for Design Space ExplorationSamit Chaudhuri, Robert A. Walker. 234-235 [doi]
- Digital Neural Processing Unit for Electronic NoseHoda S. Abdel-Aty-Zohdy, Mahmoud Al-Nsour. 236-237 [doi]
- A Low Power Charge-Recycling CMOS Clock BufferXiaohui Wang, Wolfgang Porod. 238-239 [doi]
- A Multiple-Input Single-Phase Clock Flip-Flop FamilyRichard F. Hobson, Allan R. Dyck. 240-241 [doi]
- Methodology of Logic Synthesis for Implementation Using Heterogeneous LUT FPGAsIgor Lemberski. 242-243 [doi]
- VHDL Design of a Test Processor Based on Mixed-Mode Test GenerationMd. Altaf-Ul-Amin, Zahari Mohamed Darus. 244 [doi]
- An Incremental FloorplannerJim E. Crenshaw, Majid Sarrafzadeh, Prithviraj Banerjee, Pradeep Prabhakaran. 248-251 [doi]
- A Greedy Router with Technology Targetable OutputR. Balakrishnan, Richard F. Hobson. 252-255 [doi]
- Routability Prediction for Hierarchical FPGAsWei Li, Dilip K. Banerji. 256-259 [doi]
- Memory Unit Design for Real Time DSP ApplicationsDaniel Chillet, Olivier Sentieys, Michel Corazza. 260 [doi]
- Design Automation of MEMS Systems Using Behavioral ModelingDennis Gibson, Carla N. Purdy, Alva Hare, Fred R. Beyette Jr.. 266-269 [doi]
- Blending Symbolic Matrix and Dimensional Numerical Simulation Methodology for Mechatronics SystemsRobert L. Ewing. 270-273 [doi]
- Numerical Tools for Fracture of MEMS DevicesN. Tayebi, A. K. Tayebi, Y. Belkacemi. 274 [doi]
- Formal Checking of Properties in Complex Systems Using AbstractionsDinos Moundanos, Jacob A. Abraham. 280-283 [doi]
- A Hierarchical Approach to the Formal Verification of Embedded Systems Using MDGsSubhashini Balakrishnan, Sofiène Tahar. 284-287 [doi]
- Symbolic Multi-Level Verification of RefinementStefan Hendricx, Luc J. M. Claesen. 288-291 [doi]
- Self-Checking of FPGA-Based Control UnitsIlya Levin, Vladimir Sinelnikov. 292-295 [doi]
- A Software Acceptance Testing Technique Based on Knowledge AccumulationYi Yu, Fangmei Wu. 296-299 [doi]
- A Correlation Matrix Method of Clock Partitioning for Sequential Circuit TestabilityYong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal. 300 [doi]
- A Novel Low Power Low Phase-Noise PLL Architecture for Wireless TransceiversAmr N. Hafez, Mohamed I. Elmasry. 306-309 [doi]
- NMOS Energy Recovery LogicChulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang. 310-313 [doi]
- Noise Immunity of Digital Circuits in Mixed-Signal Smart Power SystemsRadu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman. 314-317 [doi]
- An all Digital BiCMOS Phase Lock Loop for VLSI ProcessorsLim Chu Aun, S. M. Rezaul Hasan. 318-320 [doi]
- Low Power Techniques for Digital GaAs VLSIJosé Francisco López, Roberto Sarmiento, Antonio Núñez, Kamran Eshraghian, Stefan Lachowicz, Derek Abbott. 321-324 [doi]
- A VLSI Architecture for ATM Algorithm-Agile EncryptionAmr G. Wassal, M. Anwarul Hasan. 325 [doi]
- On an Efficient Method for Estimating the Interconnection Complexity of Designs and on the Existence of Region III in Rent s RuleDirk Stroobandt. 330-331 [doi]
- Monolithic Microprocessor and RF Transceiver in 0.25-micron FDSOI CMOSErik A. McShane, Krishna Shenai, Leon Alkalai, E. Kolawa, V. Boyadzhyan, B. Blaes, Wai-Chi Fang. 332-333 [doi]
- Low Power Design of an Acoustic Echo Canceller Gmdf a Algorithm on Dedicated VLSI ArchitecturesS. Gailhard, Nathalie Julien, Adel Baganne, Eric Martin. 334-335 [doi]
- Proposal of Data-Driven Processor Architecture Qv-K1Teruhiko Kamigata, Koso Murakami, Makoto Iwata, Hiroaki Terada. 336-337 [doi]
- Accurate Resource Estimation Algorithms for Behavioral SynthesisSrinivas Katkoori, Ranga Vemuri. 338-339 [doi]
- Assessing Defect Coverage of Memory Testing AlgorithmsVon-Kyoung Kim, Tom Chen. 340 [doi]
- Exploiting Test Resource Optimization in Data Path Synthesis for BISTXiaowei Li, Paul Y. S. Cheung. 342-343 [doi]
- Resonant Tunneling Transistors for Threshold Logic Circuit ApplicationsChristian Pacha, Peter Glösekötter, Karl Goser, U. Auer, W. Prost, F.-J. Tegude. 344-345 [doi]
- A Multilevel Cache Memory Architecture for NanoelectronicsDavid Crawley. 346 [doi]
- ALPS: A Peak Power Estimation Tool for Sequential CircuitsFulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 350-353 [doi]
- Clustered Table-Based Macromodels for RTL Power EstimationRoberto Corgnati, Enrico Macii, Massimo Poncino. 354-357 [doi]
- The Design of Cmos Gigahertz-Band Continuous-Time Active Lowpass Filters with Q-Enhancement CircuitsYuyu Chang, John Choma Jr., Jack Wills. 358-361 [doi]
- A New Algorithm for RNS Magnitude Comparison Based on New Chinese Remainder Theorem IIYuke Wang, Xiaoyu Song, El Mostapha Aboulhamid. 362 [doi]
- Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book MethodSatoshi Komatsu, Makoto Ikeda, Kunihiro Asada. 368-371 [doi]
- A 1.8V High Dynamic-Range CMOS High-Speed Four Quadrant MultiplierChi-Hung Lin, Mohammed Ismail. 372-375 [doi]
- A Second-Order Sigma-Delta Modulator with Built-in VGA to Improve SNR and Harmonic DistortionXiaopeng Li, Mohammed Ismail. 376-379 [doi]
- A Novel Low Power Energy Recovery Full Adder CellR. Shalem, Lizy Kurian John, Eugene John. 380 [doi]
- Memory Chip BIST ArchitectureJacob Savir. 384 [doi]
- A Fully Pipelined, 700MBytes/s DES Encryption CoreIhn Kim, Craig S. Steele, Jefferey G. Koller. 386 [doi]
- Transistor Stuck-Open Fault Detection in Multilevel CMOS CircuitsMostafa H. Abd-El-Barr, Yanging Xu, Carl McCrosky. 388 [doi]
- Advances Toward Molecular-Scale Electronic Digital Logic Circuits: A Review and ProspectusJames C. Ellenbogen. 392 [doi]
- Transport in Split Gate MOS Quantum Dot StructuresStephen Marshall Goodnick, Jonathan P. Bird, David K. Ferry, Allen D. Gunther, Maroun D. Khoury, Michael Kozicki, M. J. Rack, T. J. Thornton, D. Vasileska-Kafedezka. 394 [doi]