Journal: IEEE Trans. VLSI Syst.

Volume 26, Issue 9

1613 -- 1626Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang 0001, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng 0001. Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization
1627 -- 1636Samuel N. Pagliarini, Mehmet Meric Isgenc, Mayler G. A. Martins, Lawrence T. Pileggi. Application and Product-Volume-Specific Customization of BEOL Metal Pitch
1637 -- 1646Tsung-Han Tsai, Shih-Wei Chen. Single-Chip Design for Intelligent Surveillance System
1647 -- 1658Mahmood J. Azhar, Fathi Amsaad, Selçuk Köse. Duty-Cycle-Based Controlled Physical Unclonable Function
1659 -- 1670Hasan Erdem Yantir, Ahmed M. Eltawil, Fadi J. Kurdahi. A Two-Dimensional Associative Processor
1671 -- 1684Jinyang Li 0002, Yongpan Liu, Hehe Li, Zhe Yuan, Chenchen Fu, Jinshan Yue, Xiaoyu Feng, Chun Jason Xue, Jingtong Hu, Huazhong Yang. PATH: Performance-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors
1685 -- 1698Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee. Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions
1699 -- 1712Neetu Jindal, Preeti Ranjan Panda, Smruti R. Sarangi. Reusing Trace Buffers as Victim Caches
1713 -- 1726Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau. GPU NTC Process Variation Compensation With Voltage Stacking
1727 -- 1736Jheng-Hao Ye, Ming-Der Shieh. Low-Complexity VLSI Design of Large Integer Multipliers for Fully Homomorphic Encryption
1737 -- 1749Tahmid Abtahi, Colin Shea, Amey M. Kulkarni, Tinoosh Mohsenin. Accelerating Convolutional Neural Network With FFT on Embedded Hardware
1750 -- 1762Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar. Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification
1763 -- 1776Hong Zhang 0009, Junqiang Sun, Jie Zhang 0039, Ruizhi Zhang, Anthony Chan Carusone. A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing
1777 -- 1787Kenichi Ohhata, Daiki Hayakawa, Kenji Sewaki, Kento Imayanagida, Kouki Ueno, Yuuki Sonoda, Kenichiro Muroya. A 900-MHz, 3.5-mW, 8-bit Pipelined Subranging ADC Combining Flash ADC and TDC
1788 -- 1801Moataz Abdelfattah, Gordon W. Roberts. Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time-Mode Signal Processing
1802 -- 1806JuHyung Hong, Sangwoo Han, Young-Min Park, Eui-Young Chung. ICS: Interrupt-Based Channel Sneaking for Maximally Exploiting Die-Level Parallelism of NAND Flash-Based Storage Devices
1807 -- 1811Cecilia Gimeno, David Bol, Denis Flandre. Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits
1812 -- 1816Meysam Akbari, Omid Hashemipour, Farshad Moradi. Input Offset Estimation of CMOS Integrated Circuits in Weak Inversion

Volume 26, Issue 8

1413 -- 1426Ben Perach, Shlomo Weiss. SiMT-DSP: A Massively Multithreaded DSP Architecture
1427 -- 1437Davide Giri, Giovanni Causapruno, Fabrizio Riente. Parallel and Serial Computation in Nanomagnet Logic: An Overview
1438 -- 1451Thierry Bonnoit, Nacer-Eddine Zergainoh, Michael Nicolaidis. Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance
1452 -- 1460Nicola Lupo, Edoardo Bonizzoni, Eduardo Pérez, Christian Wenger, Franco Maloberti. A Voltage-Time Model for Memristive Devices
1461 -- 1470Anant Kulkarni, Sanjay Prajapati, Brajesh Kumar Kaushik. Transmission Coefficient Matrix Modeling of Spin-Torque-Based $n$ -Qubit Architecture
1471 -- 1480M. Hassan Najafi, David J. Lilja, Marc D. Riedel, Kia Bazargan. Low-Cost Sorting Network Circuits Using Unary Processing
1481 -- 1493Hamed Naseri, Somayeh Timarchi. Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates
1494 -- 1507Mario Donato Marino. Architectural Impacts of RFiop: RF to Address I/O Pad and Memory Controller Scalability
1508 -- 1517Mohammad Nasim Imtiaz Khan, Anirudh Iyengar, Swaroop Ghosh. Novel Magnetic Burn-In for Retention and Magnetic Tolerance Testing of STTRAM
1518 -- 1530Che-Wei Tsao, Yuan-Hao Chang, Tei-Wei Kuo. Boosting NVDIMM Performance With a Lightweight Caching Algorithm
1531 -- 1544Donald Kline Jr., Haifeng Xu, Rami G. Melhem, Alex K. Jones. Racetrack Queues for Extremely Low-Energy FIFOs
1545 -- 1553Daiguo Xu, Lei Qiu 0002, Zhengping Zhang, Tao Liu, Lu Liu, Kairang Chen, Shiliu Xu. A Linearity-Improved 8-bit 320-MS/s SAR ADC With Metastability Immunity Technique
1554 -- 1564Shunli Ma, Ning Li 0007, Junyan Ren. A 5-to-8-GHz Wideband Miniaturized Dielectric Spectroscopy Chip With $I/Q$ Mismatch Calibration in 65-nm CMOS
1565 -- 1574Zemin Liu, Yu-Pin Hsu, Bassem Fahs, Mona Mostafa Hella. An RF-DC Converter IC With On-Chip Adaptive Impedance Matching and 307- $\mu$ W Peak Output Power for Health Monitoring Applications
1575 -- 1579Qiang Liu 0011, Jia Liu, Ruoyu Sang, Jiajun Li, Tao Zhang 0025, Qijun Zhang. Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method
1580 -- 1584Xin Zhan, Joseph Riad, Peng Li, Edgar Sánchez-Sinencio. Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint
1585 -- 1589Yan Li, Yufeng Li, Jie Han 0001, JianHao Hu, Fan Yang 0001, Xuan Zeng 0001, Bruce F. Cockburn, Jie Chen 0002. Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy
1590 -- 1594Mehdi Safarpour, Reza Inanlou, Mostafa Charmi, Omid Shoaei, Olli Silvén. ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition
1595 -- 1599Ayad Dalloo, Ardalan Najafi, Alberto García Ortiz. Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
1600 -- 1603Yeongkyo Seo, Kaushik Roy 0001. High-Density SOT-MRAM Based on Shared Bitline Structure
1604 -- 1608Suganthi Venkatachalam, Seok-Bum Ko. Approximate Sum-of-Products Designs Based on Distributed Arithmetic
1609 -- 1612Leonardo Rezende Juracy, Matheus T. Moreira, Felipe A. Kuentzer, Alexandre M. Amory. A DfT Insertion Methodology to Scannable Q-Flop Elements

Volume 26, Issue 7

1209 -- 1222Ping-Lin Yang, Malgorzata Marek-Sadowska. High-Performance Architecture Using Fast Dynamic Reconfigurable Accelerators
1223 -- 1232Govinda Sannena, Bishnu Prasad Das. Low Overhead Warning Flip-Flop Based on Charge Sharing for Timing Slack Monitoring
1233 -- 1240Cheng-Hung Lin, Sze-Chen Cho, Shih-Chieh Chang. An Adaptive Mechanism for Designing Efficient Snoop Filters
1241 -- 1253Jaemin Kim, Donkyu Baek, Caiwen Ding, Sheng Lin, Donghwa Shin, Xue Lin, Yanzhi Wang, Youngjin Cho, Sang-Hyun Park, Naehyuck Chang. Dynamic Reconfiguration of Thermoelectric Generators for Vehicle Radiators Energy Harvesting Under Location-Dependent Temperature Variations
1254 -- 1267Hayate Okuhara, Akram Ben Ahmed, Johannes Maximilian Kühn, Hideharu Amano. Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization
1268 -- 1276Yu Lei, Houpeng Chen, Xiaoyun Li, Xi Li, Qian Wang, Qi Zhang, Jie Miao, Zhitang Song. A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM
1277 -- 1289Xiaowei Chen, Seyed Alireza Pourbakhsh, Jingyan Fu, Na Gong, Jinhui Wang. A Novel Hybrid Delay Unit Based on Dummy TSVs for 3-D On-Chip Memory
1290 -- 1300Manqing Mao, Shimeng Yu, Chaitali Chakrabarti. Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System
1301 -- 1311Yinqi Tang, Naveen Verma. Energy-Efficient Pedestrian Detection System: Exploiting Statistical Error Compensation for Lossy Memory Data Compression
1312 -- 1325Hao Zhou 0008, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng 0001. Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method
1326 -- 1339Siting Liu, Jie Han 0001. Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences
1340 -- 1353Wim Meeus, Dirk Stroobandt. Data Reuse Buffer Synthesis Using the Polyhedral Model
1354 -- 1367Yufei Ma, Yu Cao 0001, Sarma B. K. Vrudhula, Jae-sun Seo. Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA
1368 -- 1376Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Francesco Bruno Trotta. Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks
1377 -- 1390Claude Thibeault, Ghyslain Gagnon. On the Analysis and the Mitigation of Power Supply Noise and Power Distribution Network Impedance Variation for Scan-Based Delay Testing Techniques
1391 -- 1402Chun-Hsing Li, Wei-Min Wu. A Balunless Frequency Multiplier With Differential Output by Current Flow Manipulation
1403 -- 1407Lei Wang 0070, Chundong Wu, Lisong Feng, Alan Chang, Yong Lian. A Low-Power Forward and Reverse Body Bias Generator in CMOS 40 nm
1408 -- 1412Xiaobai Chen, Zhiyi Yu. A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator

Volume 26, Issue 6

1005 -- 1014Kai-Hsiang Hsu, Yung-Chih Chen, You-Luen Lee, Shih-Chieh Chang. Contactless Testing for Prebond Interposers
1015 -- 1025Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung. All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate
1026 -- 1039Biswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya. Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks
1040 -- 1050Sumitha George, Xueqing Li, Minli Julie Liao, Kaisheng Ma, Srivatsa Rangachar Srinivasa, Karthik Mohan, Ahmedullah Aziz, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan. Symmetric 2-D-Memory Access to Multidimensional Data
1051 -- 1058Leila Bagheriye, Siroos Toofan, Roghayeh Saeidi, Farshad Moradi. Offset-Compensated High-Speed Sense Amplifier for STT-MRAMs
1059 -- 1072Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón. Performance and Energy-Efficient Design of STT-RAM Last-Level Cache
1073 -- 1083Zhangqing He, Meilin Wan, Jie Deng, Chuang Bai, Kui Dai. A Reliable Strong PUF Based on Switched-Capacitor Circuit
1084 -- 1097Fatemeh Tehranipoor, Paul A. Wortman, Nima Karimian, Wei Yan 0005, John A. Chandy. DVFT: A Lightweight Solution for Power-Supply Noise-Based TRNG Using Dynamic Voltage Feedback Tuning System
1098 -- 1111Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang. Stream Processing Dual-Track CGRA for Object Inference
1112 -- 1125Wenbin Xu, Sachin S. Sapatnekar, Jiang Hu. A Simple Yet Efficient Accuracy-Configurable Adder Design
1126 -- 1138Jun Liu 0038, Beomsoo Park, Marino Guzman, Ahmed Fahmy, Taewook Kim, Nima Maghari. A Fully Synthesized 77-dB SFDR Reprogrammable SRMC Filter Using Digital Standard Cells
1139 -- 1150Chung-Shiang Wu, Makoto Takamiya, Takayasu Sakurai. Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes
1151 -- 1158Dong Soo Lee, Sung Jin Kim, Donggyu Kim, YoungGun Pu, Sang-Sun Yoo, MinJae Lee, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee. A Design of Fast-Settling, Low-Power 4.19-MHz Real-Time Clock Generator With Temperature Compensation and 15-dB Noise Reduction
1159 -- 1170Donghwa Shin, Massimo Poncino, Enrico Macii. Thermal Management of Batteries Using Supercapacitor Hybrid Architecture With Idle Period Insertion Strategy
1171 -- 1182Yutong Ying, Xuefei Bai, Fujiang Lin. A 1-Gb/s 6-10-GHz, Filterless, Pulsed UWB Transmitter With Symmetrical Waveform Analysis and Generation
1183 -- 1191Shanker Shreejith, Libin K. Mathew, A. Prasad Vinod, Suhaib A. Fahmy. Efficient Spectrum Sensing for Aeronautical LDACS Using Low-Power Correlators
1192 -- 1203John S. Mincey, Eric C. Su, José Silva-Martínez, Christopher T. Rodenbeck. A 128-Tap Highly Tunable CMOS IF Finite Impulse Response Filter for Pulsed Radar Applications
1204 -- 1208Georgios Zervakis, Fotios Ntouskas, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi. VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits

Volume 26, Issue 5

805 -- 817Yujie Wang, Pu Chen, Jiang Hu, Guofeng Li, Jeyavijayan Rajendran. The Cat and Mouse in Split Manufacturing
818 -- 830Ujjwal Guin, Ziqi Zhou, Adit D. Singh. Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test
831 -- 840Maohua Zhu, Youwei Zhuo, Chao Wang, Wenguang Chen, Yuan Xie 0001. Performance Evaluation and Optimization of HBM-Enabled GPU for Data-Intensive Applications
841 -- 854Jaeha Kung, Duckhwan Kim 0001, Saibal Mukhopadhyay. Adaptive Precision Cellular Nonlinear Network
855 -- 866Jaemin Kim, Donghwa Shin, Nam Ik Cho, Byunghee Kang, Naehyuck Chang. Aging Management Using a Reconfigurable Switch Network for Arrays of Nonideal Power Cells
867 -- 877Mohammad Fardad, Sayed Masoud Sayedi, Ehsan Yazdian. Hardware Implementation of Iterative Method With Adaptive Thresholding for Random Sampling Recovery of Sparse Signals
878 -- 891Md. Hasanuzzaman, Bahareh Ghane Motlagh, Fayçal Mounaïm, Ahmad Hassan, Rabin Raut, Mohamad Sawan. Toward an Energy-Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator
892 -- 902Qiong Wei Low, Mi Zhou, Liter Siek. A Single-Stage Direct-Conversion AC-DC Converter for Inductively Powered Application
903 -- 911Jiann-Jong Chen, Yuh-Shyan Hwang, Jianhan Chen, Yi-Tsen Ku, Cheng-Chieh Yu. 2-Controlled Techniques
912 -- 923Hsueh-Ling Yu, Yih-Lang Li, Tzu-Yi Liao, Tianchen Wang, Shu-Fei Tsai, Yiyu Shi. Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits
924 -- 932Thinh H. Pham, A. Prasad Vinod, A. S. Madhukumar. A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications
933 -- 944Zhao Zhang 0004, Jincheng Yang, Liyuan Liu, Peng Feng, Jian Liu, Nanjian Wu. A 0.9-2.25-GHz Sub-0.2-mW/GHz Compact Low-Voltage Low-Power Hybrid Digital PLL With Loop Bandwidth-Tracking Technique
945 -- 957Yu-Kai Tsai, Yi-Keng Hsieh, Hung-Yu Tsai, Huan-Sheng Chen, Liang-Hung Lu. A Concurrent Dual-Band and Dual-Mode Frequency Synthesizer for Radar Systems
958 -- 968Dong Wang 0006, Pak Kwong Chan. An Electrical Model for Nanometer CMOS Device Stress Effect in Design and Simulation of Analog Reference Circuits
969 -- 980Chase Cook, Zeyu Sun, Ertugrul Demircan, Mehul D. Shroff, Sheldon X.-D. Tan. Fast Electromigration Stress Evolution Analysis for Interconnect Trees Using Krylov Subspace Method
981 -- 990Jürgen Freudenberger, Mohammed Rajab, Sergo Shavgulidze. A Source and Channel Coding Approach for Improving Flash Memory Endurance
991 -- 994Jing Guo 0004, Lei Zhu, Yu Sun, Huiliang Cao, Hai Huang, Tianqi Wang, Chunhua Qi, Rongsheng Zhang, Xuebing Cao, Liyi Xiao, Zhigang Mao. Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications
995 -- 999Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian. High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure
1000 -- 1004Supriya Chakraborty, Tinish Bhattacharya, Manan Suri. Current Optimized Coset Coding for Efficient RRAM Programming

Volume 26, Issue 4

609 -- 620Hanwool Jeong, Tae-Woo Oh, Seung Chul Song, Seong-Ook Jung. Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation
621 -- 629Jen-Chieh Liu, Chao-Jen Huang, Pei-Ying Lee. A High-Accuracy Programmable Pulse Generator With a 10-ps Timing Resolution
630 -- 638Karim Ali 0004, Fei Li, Sunny Y. H. Lua, Chun-Huat Heng. Energy- and Area-Efficient Spin-Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture
639 -- 652Ivan Ratkovic, Oscar Palomar, Milan Stanic, Osman Sabri Unsal, Adrián Cristal, Mateo Valero. Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add
653 -- 662Pawan Agarwal, Jong-Hoon Kim, Partha Pratim Pande, Deukhyoun Heo. Zero-Power Feed-Forward Spur Cancelation for Supply-Regulated CMOS Ring PLLs
663 -- 670Ing-Jer Huang, Chun-Hung Lai, Yun-Chung Yang, Hsu-Kang Dow, Hung-Lun Chen. A Reconfigurable Cache for Efficient Use of Tag RAM as Scratch-Pad Memory
671 -- 683Srivatsa Rangachar Srinivasa, Xueqing Li, Meng-Fan Chang, John Sampson, Sumeet Kumar Gupta, Vijaykrishnan Narayanan. Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration
684 -- 696Dongliang Chen, Jonathon Edstrom, Yifu Gong, Peng Gao, Lei Yang, Mark E. McCourt, Jinhui Wang, Na Gong. Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory
697 -- 710Mario Donato Marino, Kuan-Ching Li. RAMON: Region-Aware Memory Controller
711 -- 719Albert Ciprut, Eby G. Friedman. Energy-Efficient Write Scheme for Nonvolatile Resistive Crossbar Arrays With Selectors
720 -- 732Haihua Shen, Huazhe Tan, Huawei Li, Feng Zhang, Xiaowei Li. LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection
733 -- 743Wenjie Che, Fareena Saqib, Jim Plusquellic. Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF
744 -- 755Zimu Guo, Xiaolin Xu, Md. Tauhidur Rahman, Mark M. Tehranipoor, Domenic Forte. SCARe: An SRAM-Based Countermeasure Against IC Recycling
756 -- 767Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez. A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS
768 -- 777Cuiping Shao, Huiyun Li. Identifying Single-Event Transient Location Based on Compressed Sensing
778 -- 791Katayoun Neshatpour, Wayne Burleson, Amin Khajeh, Houman Homayoun. Enhancing Power, Performance, and Energy Efficiency in Chip Multiprocessors Exploiting Inverse Thermal Dependence
792 -- 802Hakki Mert Torun, Madhavan Swaminathan, Anto Kavungal Davis, Mohamed Lamine Faycal Bellaredj. A Global Bayesian Optimization Algorithm and Its Application to Integrated System Design

Volume 26, Issue 3

421 -- 430Vasileios Leon, Georgios Zervakis, Dimitrios Soudris, Kiamal Z. Pekmestzi. Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers
431 -- 444Aiwen Luo, Fengwei An, Xiangyu Zhang, Lei Chen 0001, Hans Jürgen Mattausch. Resource-Efficient Object-Recognition Coprocessor With Parallel Processing of Multiple Scan Windows in 65-nm CMOS
445 -- 456Alok Prakash, Christopher T. Clarke, Siew Kei Lam, Thambipillai Srikanthan. Rapid Memory-Aware Selection of Hardware Accelerators in Programmable SoC Design
457 -- 469Anteneh Gebregiorgis, Mehdi Baradaran Tahoori. Fine-Grained Energy-Constrained Microprocessor Pipeline Design
470 -- 483Shubham Jain, Ashish Ranjan, Kaushik Roy 0001, Anand Raghunathan. Computing in Memory With Spin-Transfer Torque Magnetic RAM
484 -- 495Linuo Xue, Bi-Wu, Beibei Zhang, Yuanqing Cheng, Peiyuan Wang, Chando Park, Jimmy Kan, Seung H. Kang, Yuan Xie 0001. An Adaptive 3T-3MTJ Memory Cell Design for STT-MRAM-Based LLCs
496 -- 507Huyen Thi Pham, Hanho Lee. Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields
508 -- 521Thien Truong Nguyen-Ly, Valentin Savin, Khoa LeTrung, David Declercq, Fakhreddine Ghaffari, Oana Boncalo. Analysis and Design of Cost-Effective, High-Throughput LDPC Decoders
522 -- 530Ja-Hoon Jin, Seok Kim, Xuefan Jin, Sang-Hoon Kim, Jung-Hoon Chun. A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique
531 -- 543Shengcheng Wang, Taeyoung Kim 0001, Zeyu Sun, Sheldon X.-D. Tan, Mehdi Baradaran Tahoori. Recovery-Aware Proactive TSV Repair for Electromigration Lifetime Enhancement in 3-D ICs
544 -- 557Ganapati Bhat, Gaurav Singla, Ali K. Unver, Ümit Y. Ogras. Algorithmic Optimization of Thermal and Power Management for Heterogeneous Mobile Platforms
558 -- 571Vineeth Sarma, Rahul Thottathil, Bibhu Datta Sahoo. A DC-to-1-GHz Continuously Tunable Bandpass ADC
572 -- 583Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu 0001, Seng-Pan U. A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS
584 -- 588Chunyu Peng, Songsong Xiao, Wenjuan Lu, Jingbo Zhang, Xiulong Wu, Junning Chen, Zhiting Lin. Average 7T1R Nonvolatile SRAM With R/W Margin Enhanced for Low-Power Application
589 -- 593Peeyoosh Mirajkar, Jagdish Chand, Sankaran Aniruddhan, Srinivas Theertham. Low Phase Noise Ku-Band VCO With Optimal Switched-Capacitor Bank Design
594 -- 598Xuan Dong, Lihong Zhang. Analog Layout Retargeting With Process-Variation-Aware Hybrid OPC
599 -- 603Arya Balachandran, Yong Chen, Chirn Chye Boon. 2 0.53-mW/Gb/s 32-Gb/s Hybrid Analog Equalizer Under 21-dB Channel Loss in 65-nm CMOS
604 -- 607Sahil Shah, Hakan Toreyin, Jennifer Hasler, Aishwarya Natarajan. Temperature Sensitivity and Compensation on a Reconfigurable Platform

Volume 26, Issue 2

221 -- 229Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Costas Argyrides, Jie Li. Extending 3-bit Burst Error-Correction Codes With Quadruple Adjacent Error Correction
230 -- 238Kazuteru Namba, Fabrizio Lombardi. On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency Reduction
239 -- 248Shaoyi Peng, Han Zhou, Taeyoung Kim, Hai-Bao Chen, Sheldon X.-D. Tan. Physics-Based Compact TDDB Models for Low-k BEOL Copper Interconnects With Time-Varying Voltage Stressing
249 -- 261Mohammad Khavari Tavana, Mohammad Hossein Hajkazemi, Divya Pathak, Ioannis Savidis, Houman Homayoun. ElasticCore: A Dynamic Heterogeneous Platform With Joint Core and Voltage/Frequency Scaling
262 -- 271Jui-Hung Hsieh, Hung Ren Wang. VLSI Design of an ML-Based Power-Efficient Motion Estimation Controller for Intelligent Mobile Systems
272 -- 279Albert Lee, Hochul Lee, Farbod Ebrahimi, Bonnie Lam, Wei-Hao Chen, Meng-Fan Chang, Pedram Khalili Amiri, Kang-Lung Wang. A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories
280 -- 293Yizhi Wang, Jun Lin, Zhongfeng Wang. An Energy-Efficient Architecture for Binary Weight Convolutional Neural Networks
294 -- 307Arnab Raha, Akhilesh Jaiswal, Syed Shakib Sarwar, Hrishikesh Jayakumar, Vijay Raghunathan, Kaushik Roy 0001. Designing Energy-Efficient Intermittently Powered Systems Using Spin-Hall-Effect-Based Nonvolatile SRAM
308 -- 318Reza Sharafinejad, Bijan Alizadeh, Zainalabedin Navabi. Automatic Correction of Dynamic Power Management Architecture in Modern Processors
319 -- 328Sujuan Liu, Ning Lyu, Haojiang Wang. The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection
329 -- 340Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg. A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
341 -- 354Aryan Tavakkoli, David B. Thomas. A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers
355 -- 366Rahul Gharpinde, Phrangboklang Lynton Thangkhiew, Kamalika Datta, Indranil Sengupta 0001. A Scalable In-Memory Logic Synthesis Approach Using Memristor Crossbar
367 -- 377Jai Narayan Tripathi, Ramachandra Achar, Rakesh Malik. Fast Analysis of Time Interval Error in Current-Mode Drivers
378 -- 391Zhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan. m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication
392 -- 403Michael Weiner, Salvador Manich, Rosa Rodríguez-Montañés, Georg Sigl. The Low Area Probing Detector as a Countermeasure Against Invasive Attacks
404 -- 415Daniel O'Hare, Anthony G. Scanlan, Eric Thompson, Brendan Mullane. Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs
416 -- 420Yan Song, Chi-Hang Chan, Yan Zhu 0001, Li Geng, Seng-Pan U, Rui Paulo Martins. Passive Noise Shaping in SAR ADC With Improved Efficiency

Volume 26, Issue 12

2579 -- 2580Krishnendu Chakrabarty. Editorial
2581 -- 2583Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing. Guest Editorial Memristive-Device-Based Computing
2584 -- 2590Jaeyoung Park, Young Uk Yim. Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM
2591 -- 2598Kwangmin Kim, Seokjoon Kang, Jae-Yoon Sim, Hong June Park, Byungsub Kim. A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization
2599 -- 2607Alessandro Grossi, Elisa Vianello, Cristian Zambelli, Pablo Royer, Jean-Philippe Noel, Bastien Giraud, Luca Perniola, Piero Olivo, Etienne Nowak. Experimental Investigation of 4-kb RRAM Arrays Programming Conditions Suitable for TCAM
2608 -- 2618Mehri Teimoori, Amirali Amirsoleimani, Arash Ahmadi, Majid Ahmadi. A 2M1M Crossbar Architecture: Memory
2619 -- 2627Nahid Mirzaie, Ahmed Alzahmi, Hossein Shamsi, Gyung-Su Byun. Three-Dimensional Pipeline ADC Utilizing TSV/ Design Optimization and Memristor Ratioed Logic
2628 -- 2640Jinghua Yang, Aykut Dengi, Sarma B. K. Vrudhula. Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
2641 -- 2647Xiaoping Wang, Shuai Li, Zhigang Zeng. Configurable Logic Operations Using Hybrid CRS-CMOS Cells
2648 -- 2660Shuyu Kong, Hai Zhou, Jie Gu. Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design
2661 -- 2670Rekha Govindaraj, Swaroop Ghosh, Srinivas Katkoori. CSRO-Based Reconfigurable True Random Number Generator Using RRAM
2671 -- 2683Md Tanvir Arafin, Gang Qu. Memristors for Secret Sharing-Based Lightweight Authentication
2684 -- 2695Mohsen Nourazar, Vahid Rashtchi, Ali Azarpeyvand, Farshad Merrikh-Bayat. Code Acceleration Using Memristor-Based Approximate Matrix Multiplier: Application to Convolutional Neural Networks
2696 -- 2708Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu. Networked Power-Gated MRAMs for Memory-Based Computing
2709 -- 2722Yomi Karthik Rupesh, Payman Behnam, Goverdhan Reddy Pandla, Manikanth Miryala, Mahdi Nazm Bojnordi. Accelerating k-Medians Clustering Using a Novel 4T-4R RRAM Cell
2723 -- 2736Hiroyuki Ochi, Kosei Yamaguchi, Tetsuaki Fujimoto, Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Takashi Imagawa, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Wataru Takahashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Jaehoon Yu, Masanori Hashimoto. Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars
2737 -- 2748Fengyu Qian, Yanping Gong, Guoxian Huang, Mehdi Anwar, Lei Wang 0003. Exploiting Memristors for Compressive Sampling of Sensory Signals
2749 -- 2758Yasmin Halawani, Baker Mohammad, Mahmoud Al-Qutayri, Said F. Al-Sarawi. Memristor-Based Hardware Accelerator for Image Compression
2759 -- 2772Advait Madhavan, Tim Sherwood, Dmitri B. Strukov. High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing
2773 -- 2780Yasmin Halawani, Muath Abu Lebdeh, Baker Mohammad, Mahmoud Al-Qutayri, Said F. Al-Sarawi. Stateful Memristor-Based Search Architecture
2781 -- 2794Yun Long, Taesik Na, Saibal Mukhopadhyay. ReRAM-Based Processing-in-Memory Architecture for Recurrent Neural Network Acceleration
2795 -- 2805Jafar Shamsi, Karim Mohammadi, Shahriar B. Shokouhi. A Hardware Architecture for Columnar-Organized Memory Based on CMOS Neuron and Memristor Crossbar Arrays
2806 -- 2815Valerio Milo, Giacomo Pedretti, Roberto Carboni, Alessandro Calderoni, Nirmal Ramaswamy, Stefano Ambrogio, Daniele Ielmini. A 4-Transistors/1-Resistor Hybrid Synapse Based on Resistive Switching Memory (RRAM) Capable of Spike-Rate-Dependent Plasticity (SRDP)
2816 -- 2829Jason Kamran Eshraghian, Kyoung-Rok Cho, Ciyan Zheng, Minho Nam, Herbert Ho-Ching Iu, Wen Lei, Kamran Eshraghian. Neuromorphic Vision Hybrid RRAM-CMOS Architecture
2830 -- 2841Liuting Shang, Shukai Duan, Lidan Wang, Tingwen Huang. SRMC: A Multibit Memristor Crossbar for Self-Renewing Image Mask
2842 -- 2852Hsin-Pei Wang, Chia-Chun Lin, Chia-Cheng Wu, Yung-Chih Chen, Chun-Yao Wang. On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses
2853 -- 2862Ming Ding, Pieter Harpe, Guibin Chen, Benjamin Busze, Yao-Hong Liu, Christian Bachmann, Kathleen Philips, Arthur H. M. van Roermund. A Hybrid Design Automation Tool for SAR ADCs in IoT
2863 -- 2872Zhongyi Fu, Kong-Pang Pun. An SAR ADC Switching Scheme With MSB Prediction for a Wide Input Range and Reduced Reference Voltage
2873 -- 2883Arpan Thakkar, Srinivas Theertham, Sankaran Aniruddhan. Phase Noise Analysis of Bipolar Class-C VCOs With Delay in Oscillator Loop
2884 -- 2897Arnab Raha, Vijay Raghunathan. Approximating Beyond the Processor: Exploring Full-System Energy-Accuracy Tradeoffs in a Smart Camera System
2898 -- 2906Po-Hung Chen, Hao-Chung Cheng, Yi-An Ai, Wang-Ting Chung. Automatic Mode-Selected Energy Harvesting Interface With >80% Power Efficiency Over 200 nW to 10 mW
2907 -- 2920Sravan K. Marella, Sachin S. Sapatnekar. Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs
2921 -- 2934Srinivasan Gopal, Sourav Das, Pawan Agarwal, Sheikh Nijam Ali, Deukhyoun Heo, Partha Pratim Pande. High-Performance and Small-Form Factor Near-Field Inductive Coupling for 3-D NoC
2935 -- 2946Ahmet Turan Erozan, Gabriel Cadilha Marques, Mohammad Saber Golanbari, Rajendra Bishnoi, Simone Dehm, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori. Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication
2947 -- 2954Arturo Buscarino, Claudia Corradino, Luigi Fortuna, Leon O. Chua. Taming Spatiotemporal Chaos in Forced Memristive Arrays

Volume 26, Issue 11

2195 -- 2204Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty. Trident: Comprehensive Choke Error Mitigation in NTC Systems
2205 -- 2216Shengyu Duan, Mark Zwolinski, Basel Halak. Lifetime Reliability-Aware Digital Synthesis
2217 -- 2229Yutaka Masuda, Takao Onoye, Masanori Hashimoto. Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
2230 -- 2240Divya Pathak, Ioannis Savidis. On-Chip Power Supply Noise Suppression Through Hyperabrupt Junction Varactors
2241 -- 2253Teng Yang, Doyun Kim, Jiangyi Li, Peter R. Kinget, Mingoo Seok. In~Situ and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files
2254 -- 2267Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy. A Repair-for-Diagnosis Methodology for Logic Circuits
2268 -- 2278Hamed Zandevakili, Ali Mahani. A New ASIC Structure With Self-Repair Capability Using Field-Programmable Nanowire Interconnect Architecture
2279 -- 2289Guan-Cheng Wang, Yan Zhu 0001, Chi-Hang Chan, Seng-Pan U, Rui P. Martins. Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
2290 -- 2298Chutham Sawigun, Surachoke Thanapitak. rms IRN Low-Pass Filter for ECG Acquisition Using FVF Biquads
2299 -- 2309F. N. U. Juanda, Wei Shu, Joseph S. Chang. A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme
2310 -- 2321Youngwoo Ji, Byungsub Kim, Hong June Park, Jae-Yoon Sim. A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation
2322 -- 2334Shuo-Han Chen, Yen-Ting Chen, Yuan-Hao Chang, Hsin-Wen Wei, Wei Kuan Shih. A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND Flash
2335 -- 2344Makoto Yabuuchi, Yasumasa Tsukamoto, Hidehiro Fujiwara, Miki Tanaka, Shinji Shinji, Koji Nii. A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures
2345 -- 2357Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei. Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM
2358 -- 2371Jiangwei Zhang, Donald Kline Jr., Liang Fang, Rami G. Melhem, Alex K. Jones. Data Block Partitioning Methods to Mitigate Stuck-At Faults in Limited Endurance Memories
2372 -- 2385Awny M. El-Mohandes, Ahmed Shalaby, Mohammed S. Sayed. Efficient Low-Power Digital Baseband Transceiver for IEEE 802.15.6 Narrowband Physical Layer
2386 -- 2394Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández. A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design
2395 -- 2405Dimo Martev, Sven Hampel, Ulf Schlichtmann. Automated Phase-Noise-Aware Design of RF Clock Distribution Circuits
2406 -- 2418Joe Baylon, Xinmin Yu, Srinivasan Gopal, Reza Molavi, Shahriar Mirabbasi, Partha Pratim Pande, Deukhyoun Heo. A 16-Gb/s Low-Power Inductorless Wideband Gain-Boosted Baseband Amplifier With Skewed Differential Topology for Wireless Network-on-Chip
2419 -- 2430Xin Cai, Mingda Zhou, Tian Xia, Wai H. Fong, Wing-Tsz Lee, Xinming Huang 0001. Low-Power SDR Design on an FPGA for Intersatellite Communications
2431 -- 2442Xiaolin Xu, Shahrzad Keshavarz, Domenic Forte, Mark M. Tehranipoor, Daniel E. Holcomb. Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs
2443 -- 2455Mimi Xie, Shuangchen Li, Alvin Oliver Glova, Jingtong Hu, Yuan Xie 0001. Securing Emerging Nonvolatile Main Memory With Fast and Energy-Efficient AES In-Memory Implementation
2456 -- 2469Dongrong Zhang, Xiaoxiao Wang, Md. Tauhidur Rahman, Mark Tehranipoor. An On-Chip Dynamically Obfuscated Wrapper for Protecting Supply Chain Against IP and IC Piracies
2470 -- 2482Kexin Yang, Taizhi Liu, Rui Zhang, Linda Milor. A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology
2483 -- 2493Hengyang Zhao, Sheldon X.-D. Tan. Postvoiding FEM Analysis for Electromigration Failure Characterization
2494 -- 2503Xiaoyuan Qi, Raymond J. Rosner, John Hopkins, Jack M. Higman, Rick Mewhirter, Aaron Sinnott, Binod Kumar G. Nair, Ishtiaq Ahsan, Mark Lagus. A Simplified Yield Model for SRAM Repair in Advanced Technology
2504 -- 2517Xingquan Li, Bei Yu 0001, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu. Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP
2518 -- 2529Wai-Kong Lee, Ramachandra Achar, Michel S. Nakhla. Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation
2530 -- 2541Masoud Pashaeifar, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. Approximate Reverse Carry Propagate Adder for Energy-Efficient DSP Applications
2542 -- 2552Parham Hosseinzadeh Namin, Crystal Roma, Roberto Muscedere, Majid Ahmadi. Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic
2553 -- 2566Yu-Hsuan Lee, Meng-Ren Huang. Algorithm and Architecture Design of a Hardware-Efficient Frame Rate Upconversion Engine
2567 -- 2571Irith Pomeranz. Observation Points on State Variables for the Compaction of Multicycle Tests
2572 -- 2576Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Honglan Jiang, Jie Han 0001. Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error

Volume 26, Issue 10

1817 -- 1830Dennis R. E. Gnad, Fabian Oboril, Saman Kiamehr, Mehdi Baradaran Tahoori. An Experimental Evaluation and Analysis of Transient Voltage Fluctuations in FPGAs
1831 -- 1844Javad Mohebbi Najm Abad, Ali Soleimani. Novel Feature Selection Algorithm for Thermal Prediction Model
1845 -- 1853Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi. Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors
1854 -- 1867Mohammad Torabi, Lihong Zhang. Electromigration- and Parasitic-Aware ILP-Based Analog Router
1868 -- 1880Abdullah Guler, Niraj K. Jha. Hybrid Monolithic 3-D IC Floorplanner
1881 -- 1894Sukarn Agarwal, Hemangee K. Kapoor. Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches
1895 -- 1907Xian Li, Karthi Duraisamy, Paul Bogdan, Janardhan Rao Doppa, Partha Pratim Pande. Scalable Network-on-Chip Architectures for Brain-Machine Interface Applications
1908 -- 1921Mario Milicevic, P. Glenn Gulak. A Multi-Gb/s Frame-Interleaved LDPC Decoder With Path-Unrolled Message Passing in 28-nm CMOS
1922 -- 1929Tian Wang, Xiaoxin Cui, Yewen Ni, Dunshan Yu, Xiaole Cui. Evaluation of Dynamic-Adjusting Threshold-Voltage Scheme for Low-Power FinFET Circuits
1930 -- 1938Takayuki Onishi, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Ken Nakamura, Koyo Nitta, Kimiko Kawashima, Jun Okamoto, Naoki Ono, Atsushi Sagata, Hiroe Iwasaki, Mitsuo Ikeda, Atsushi Shimizu. A Single-Chip 4K 60-fps 4: 2: 2 HEVC Video Encoder LSI Employing Efficient Motion Estimation and Mode Decision Framework With Scalability to 8K
1939 -- 1952Imad Benacer, François-Raymond Boyer, Yvon Savaria. A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue
1953 -- 1966Xiaowen Chen, Yuanwu Lei, Zhonghai Lu, Shuming Chen. A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition
1967 -- 1979Waleed El-Halwagy, Pedram Mousavi, Masum Hossain. A 100-MS/s-5-GS/s, 13-5-bit Nyquist-Rate Reconfigurable Time-Domain ADC
1980 -- 1988Jian Luo 0004, Jing Li 0022, Ning Ning, Yang Liu 0062, Qi Yu. A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS
1989 -- 1998Yung-Hui Chung, Chia-Wei Yen, Pei-Kang Tsai, Bo-Wei Chen. A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme
1999 -- 2006Susie Kim, Seung-In Na, Youngtae Yang, Suhwan Kim. A 2-MHz BW 82-dB DR Continuous-Time Delta-Sigma Modulator With a Capacitor-Based Voltage DAC for ELD Compensation
2007 -- 2015Travis E. Schulze, Daryl G. Beetner, Yiyu Shi, Kevin A. Kwiat, Charles A. Kamhoua. Combating Data Leakage Trojans in Commercial and ASIC Applications With Time-Division Multiplexing and Random Encoding
2016 -- 2026Alec Roelke, Mircea R. Stan. Controlling the Reliability of SRAM PUFs With Directed NBTI Aging and Recovery
2027 -- 2037Lawrence T. Clark, Sai Bharadwaj Medapuram, Divya Kiran Kadiyala. SRAM Circuits for True Random Number Generation Using Intrinsic Bit Instability
2038 -- 2049Ata Khorami, Mohammad Sharifkhani. A Low-Power High-Speed Comparator for Precise Applications
2050 -- 2060Kyoohyun Noh, Judy M. Amanor-Boadu, Minglei Zhang, Edgar Sánchez-Sinencio. A 13.56-MHz CMOS Active Rectifier With a Voltage Mode Switched-Offset Comparator for Implantable Medical Devices
2061 -- 2072Shirin Pourashraf, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal. A Highly Efficient Composite Class-AB-AB Miller Op-Amp With High Gain and Stable From 15 pF Up To Very Large Capacitive Loads
2073 -- 2084Shila Shamsadini, Igor M. Filanovsky, Pedram Mousavi, Kambiz Moez. A 60-GHz Transmission Line Phase Shifter Using Varactors and Tunable Inductors in 65-nm CMOS Technology
2085 -- 2098Ahmad Hassan, Yvon Savaria, Mohamad Sawan. Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review
2099 -- 2107Kehan Zhu, Vishal Saxena. From Design to Test: A High-Speed PRBS
2108 -- 2117Riadul Islam, Hany Ahmed Fahmy, Ping-Yao Lin, Matthew R. Guthaus. DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis
2118 -- 2131Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu. A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design
2132 -- 2142Joaquin Gracia-Moran, Luis J. Saiz-Adalid, Daniel Gil-Tomas, Pedro J. Gil-Vicente. Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
2143 -- 2154Lizheng Liu, Yi Jin, Yi Liu 0027, Ning Ma, Yuxiang Huan, Zhuo Zou, Lirong Zheng. A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing
2155 -- 2159Pengda Huang. Study on a Low-Complexity ECG Compression Scheme With Two-Tier Sensors
2160 -- 2164Irith Pomeranz. Selecting Functional Test Sequences for Defect Diagnosis
2165 -- 2169Tejinder Singh Sandhu, Kamal El-Sankary. Beyond Rail-to-Rail Compliant Current Sources for Mismatch-Insensitive Voltage-to-Time Conversion
2170 -- 2174Youngwoo Jo, Hyojun Kim, SeongHwan Cho. A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation
2175 -- 2179Lei Qiu 0002, Chuanshi Yang, Keping Wang, Yuanjin Zheng. A High-Speed 2-bit/Cycle SAR ADC With Time-Domain Quantization
2180 -- 2184Robert Giterman, Maoz Vicentowski, Itamar Levi, Yoav Weizman, Osnat Keren, Alexander Fish. Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell
2185 -- 2189Yonghong Tao, Andreas Hierlemann. A 15-Channel 30-V Neural Stimulator for Spinal Cord Repair
2190 -- 2194Lidan Wang, Chenchang Zhan, Junyao Tang, Yang Liu 0061, Guofeng Li. A 0.9-V 33.7-ppm/°C 85-nW Sub-Bandgap Voltage Reference Consisting of Subthreshold MOSFETs and Single BJT

Volume 26, Issue 1

1 -- 10Aatreyi Bal, Shamik Saha, Sanghamitra Roy, Koushik Chakraborty. Dynamic Choke Sensing for Timing Error Resilience in NTC Systems
11 -- 22Laura Rozo, Aaron Myles Landwehr, Yan Zheng, Chengmo Yang, Guang Gao. Reliability-Aware Runtime Adaption Through a Statically Generated Task Schedule
23 -- 36Muayad J. Aljafar, Marek A. Perkowski, John M. Acken, Robin Tan. A Time-Efficient CMOS-Memristive Programmable Circuit Realizing Logic Functions in Generalized AND-XOR Structures
37 -- 49Jongho Kim, Kiyoung Choi, YongHwan Kim, Wook Kim, Kyung Tae Do, Jung Hwan Choi. Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation
50 -- 62Ing-Chao Lin, Yun Kae Law, Yuan Xie. Mitigating BTI-Induced Degradation in STT-MRAM Sensing Schemes
63 -- 72Maria Malik, Rajiv V. Joshi, Rouwaida Kanj, Shupeng Sun, Houman Homayoun, Tong Li. Sparse Regression Driven Mixture Importance Sampling for Memory Design
73 -- 81Yuntao Liu, Yang Xie, Chongxi Bao, Ankur Srivastava. A Combined Optimization-Theoretic and Side- Channel Approach for Attacking Strong Physical Unclonable Functions
82 -- 95Itamar Levi, Alexander Fish, Osnat Keren. Low-Cost Pseudoasynchronous Circuit Design Style With Reduced Exploitable Side Information
96 -- 109Adwaya Kulkarni, Adam Page, Nasrin Attaran, Ali Jafari, Maria Malik, Houman Homayoun, Tinoosh Mohsenin. An Energy-Efficient Programmable Manycore Accelerator for Personalized Biomedical Applications
110 -- 121Tosiron Adegbija, Ann Gordon-Ross. PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking
122 -- 132Yujin Park, Junghee Yun, Dongchul Park, Sangwoo Kim, Suhwan Kim. An Uncooled Microbolometer Infrared Imager With a Shutter-Based Successive-Approximation Calibration Loop
133 -- 142Jubin Mitra, Tapan Kumar Nayak. An FPGA-Based Phase Measurement System
143 -- 154Xing Wang, Derek Chi-Wai Pao. Memory-Based Architecture for Multicharacter Aho-Corasick String Matching
155 -- 167Xunzhao Yin, Behnam Sedighi, Melinda Varga, Mária Ercsey-Ravasz, Zoltán Toroczkai, Xiaobo Sharon Hu. Efficient Analog Circuits for Boolean Satisfiability
168 -- 181Sai Vineel Reddy Chittamuru, Ishan G. Thakkar, Sudeep Pasricha. HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCs
182 -- 195Ioannis Tsatsaragkos, Vassilis Paliouras. A Reconfigurable LDPC Decoder Optimized for 802.11n/ac Applications
196 -- 200Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang. Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design
201 -- 205Yang Liu, Chenchang Zhan, Lidan Wang. An Ultralow Power Subthreshold CMOS Voltage Reference Without Requiring Resistors or BJTs
206 -- 210Donghyun Kim, Hayoung Lee, Sungho Kang. An Area-Efficient BIRA With 1-D Spare Segments
211 -- 215Zhen Gao, Qingqing Jing, Yumeng Li, Pedro Reviriego, Juan Antonio Maestro. An Efficient Fault-Tolerance Design for Integer Parallel Matrix-Vector Multiplications
216 -- 220Yuh-Shyan Hwang, Jiann-Jong Chen, Rong-Lian Shih, Yi-Tsen Ku. A 2- $\mu \text{s}$ Fast-Response Step-Up Converter With Efficiency-Enhancement Techniques Suitable for Cluster-Based Wireless Sensor Networks