Table of Contents

• Mixed-Signal Design for TestBapiraju Vinnakota, Ramesh Harjani. 2 [doi]
• Low Power DesignKaushik Roy, R. K. Roy. 2 [doi]
• Register Transfer Level Synthesis: From Theory to PracticeKurt Keutzer, Sharad Malik. 2 [doi]
• Practical Test and DFT for Next Generation VLSIJacob A. Abraham, Gopi Ganapathy. 3 [doi]
• VLSI Implementation of DSP ArchitecturesA. Ratan Gupta, V. Visvanathan. 3 [doi]
• Hardware Software Co-Design of Embedded SystemsRajesh Gupta. 3 [doi]
• Science, Technology, and the Indian SocietyVishwani D. Agrawal. 6-9 [doi]
• The New Electronics IndustryThomas J. Engibou. 10 [doi]
• VLSI in Mobile CommunicationRobert W. Brodersen, Rajeev Jain. 11-13 [doi]
• Medium access control and air-interface subsystem for an indoor wireless ATM networkMani B. Srivastava. 14-18 [doi]
• Behavioral Modeling of an ATM Switch using SpecChartsA. Sriram, Fadi J. Kurdahi. 19-22 [doi]
• A Novell Allocation Strategy for Control and Memory Intensive Telecommunication CirciutsBengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen. 23-28 [doi]
• Design tradeoffs in high speed multipliers and FIR filtersChetana Nagendra, Robert Michael Owens, Mary Jane Irwin. 29-32 [doi]
• A simple yet effective genetic approach for the orientation assignment on cell-based layoutJin-Tai Yan. 33-36 [doi]
• Parallel simulated annealing strategies for VLSI cell placementJohn A. Chandy, Prithviraj Banerjee. 37-42 [doi]
• Channel routing in Manhattan-diagonal modelSandip Das, Bhargab B. Bhattacharya. 43-48 [doi]
• Routing using implicit connection graphs [VLSI designSi-Qing Zheng, Joon Shik Lim, S. Sitharama Iyengar. 49-52 [doi]
• Design for high-speed testability of stuck-at faultsTapan J. Chakraborty, Vishwani D. Agrawal. 53-56 [doi]
• A Novel BIST Architecture With Built-in Self CheckMohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar. 57-60 [doi]
• Programmable cellular automata based testbed for fault diagnosis in VLSI circuitsS. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri. 61-64 [doi]
• Hierarchical Probablistic Diagnosis of MCMs on Large-Area SubstratesKoppolu Sasidhar, Abhijit Chatterjee. 65-68 [doi]
• A novel VLSI concurrent dual multiplier-dual adder architecture for image and video coding applicationsD. V. Poornaiah, P. V. Ananda Mohan. 69-72 [doi]
• Instruction-Set Matching and GA-based Selection for Embedded-Processor Code GenerationJ. Shu, Thomas Charles Wilson, Dilip K. Banerji. 73-76 [doi]
• Instruction-Set Modeling for ASIP Code GenerationRainer Leupers, Peter Marwedel. 77-80
• CoDe-C: A Novel Two-Level Hardware/Software Co-Design FrameworkReiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig. 81-84 [doi]
• A micropower analog hearing aid on low voltage CMOS digital processA. B. Bhattacharyya, R. S. Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri. 85-89 [doi]
• A 20MHz CMOS Variable Gain AmplifierC. Srinivasan, K. Radhakrishna Rao. 90-93 [doi]
• Low-Power, Low-Voltage BiCMOS Comparators for Approximately 200MHz, 8bit OperationAndrea Boni, Carlo Morandi. 94-98 [doi]
• A Very High Gain Bandwidth Product Fully Differential AmplifierJ. Weiss, B. Majoux, Gérard Bouvier. 99-102 [doi]
• Fast Algorithms for Computer IDDQ Tests for Combination CircuitsPaul J. Thadikaran, Sreejit Chakravarty. 103-106 [doi]
• On More Efficient Combinational ATPG Using Functional LearningRajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell. 107-110 [doi]
• Sequential Circuits with combinational Test Generation ComplexityArun Balakrishnan, Srimat T. Chakradhar. 111-117 [doi]
• Genetic Algorithms for Scan Path DesignC. P. Ravikumar, Rajamani Rajarajan. 118-121 [doi]
• Allocation and Binding in Data Path Synthesis Using a Genetic Algorithm ApproachChittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose. 122-125 [doi]
• A Hierarchical Register Optimization Algorithm for Behavioral SynthesisSrinivas Katkoori, Ranga Vemuri, Jay Roy. 126-132 [doi]
• A Rule-Based Approach for Improving Allocation of Filter Structures in HLSJohnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani. 133-139 [doi]
• Representation and Synthesis of Interface of a Circuit for its ReuseSantonu Sarkar, Anupam Basu, Arun K. Majumdar. 140-145 [doi]
• Clock-Skew Constrained Cell PlacementNatesan Venkateswaran, Dinesh Bhatia. 146-149 [doi]
• On Moment-Based Metric for Optimal Termination of Transmission Line InterconnectsRohini Gupta, Byron Krauter, Lawrence T. Pileggi. 150-155 [doi]
• Combined Effect of Grain Boundary Depletion and PolySi/Oxide Interface Depletion on Drain Characteristics of a p-MOSFETR. P. Suresh, P. Venugopal, S. Tamizh Selvam, S. Potla. 156-161 [doi]
• An Analytical Delay Model Based on Boolean ProcessYinghua Min, Zhuxing Zhao, Zhongcheng Li. 162-165 [doi]
• Methods for Dynamic Test Vector compaction in Sequential Test GenerationTimothy John Lambert, Kewal K. Saluja. 166-169 [doi]
• Dynamic test Sequence compaction for Sequential CircuitsAnand Raghunathan, Srimat T. Chakradhar. 170-173 [doi]
• An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-CircuitsDhruva R. Chakrabarti, Ajai Jain. 174-177 [doi]
• Synchronous Test Generation Model for Asynchronous CircuitsSavita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy. 178-185 [doi]
• Behavioral Synthesis of Complex Parallel ControllersKrzysztof Bilinski, Erik L. Dagless, Jonathan M. Saul. 186-191 [doi]
• A Graph-Based Approach to the Synthesis of Multi-Chip Module ArchitecturesRaghava V. Cherabuddi, Jijun Chen, Magdy A. Bayoumi. 192-197 [doi]
• Synchronous Controller Models for Synthesis from Communicating VHDL ProcessesNaren Narasimhan, Ranga Vemuri, Jay Roy. 198-204 [doi]
• Synthesis of Testable Pipelined Datapaths Using Genetic SearchC. P. Ravikumar, V. Saxena. 205-210
• Bipartitioning for Hybrid FPGA-Software SimulatioA. Singla, T. M. Conte. 211-214 [doi]
• LUT-based FPGA Technology Mapping using Permissible FunctionsTakayuki Suyama, Hiroshi Sawada, Akira Nagoya. 215-218 [doi]
• VaWiRAM: a variable width random access memory moduleLizy Kurian John. 219-224 [doi]
• Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAsFran Hanchek, Shantanu Dutt. 225-229 [doi]
• Low-cost DC built-in self-test of linear analog circuits using checksumsAbhijit Chatterjee, Bruce C. Kim, Naveena Nagi. 230-233 [doi]
• Design of high performance two stage CMOS cascode op-amps with stable biasingPradip Mandal, V. Visvanathan. 234-237 [doi]
• Testing Analogue Circuits by A C Power Supply VoltageA. K. B. A ain, A. H. Bratt, A. P. Dorey. 238-241 [doi]
• Test generation for mixed-signal devices using signal flow graphsRajesh Ramadoss, Michael L. Bushnell. 242-248 [doi]
• A study of composition schemes for mixed apply/compose based construction of ROBDDsAmit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. 249-253 [doi]
• On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic CircuitsIrith Pomeranz, Sudhakar M. Reddy. 254-259 [doi]
• Does retiming affect redundancy in sequential circuits?Debesh Kumar Das, Bhargab B. Bhattacharya. 260-263 [doi]
• Cubical CAMP for minimization of Boolean functionsNripendra N. Biswas, C. Srikanth, James Jacob. 264-269 [doi]
• A VLSI architecture for cellular automata based parallel data compressionS. Bhattacharjee, J. Bhattacharya, U. Raghavendra, Debashis Saha, Parimal Pal Chaudhuri. 270-275 [doi]
• VLSI/WSI Designs for Folded Cube-Connected Cycles ArchitecturesM. P. Sebastian, P. S. Nagendra Rao, Lawrence Jenkins. 276-279 [doi]
• A tree matching chipVamsi Krishna, Abdel Ejnioui, N. Ranganathan. 280-285 [doi]
• A systolic architecture for LMS adaptive filtering with minimal adaptation delayS. Ramanathan, V. Visvanathan. 286-289 [doi]
• Statistical path delay fault coverage estimation for synchronous sequential circuitsLakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas. 290-295 [doi]
• Retiming with logic duplication transformation: theory and an application to partial scanArun Balakrishnan, Srimat T. Chakradhar. 296-302 [doi]
• Is Compiled Simulation Really Faster than Interpreted Simulation?Peter M. Maurer. 303-306 [doi]
• Distributed logic simulation: time-first evaluation vs. event driven algorithmsS. Sundaram, Lalit M. Patnaik. 307-310 [doi]
• Designing Systems On Silicon: A Digital Spread Spectrum PagerS. Samel, Bert Gyselinckx, Ivo Bolsens, Hugo De Man. 311-312 [doi]
• A high-speed 32-bit parallel correlator for spread spectrum communicationShriram Kulkarni, Pinaki Mazumder, George I. Haddad. 313-315 [doi]
• Architecture of a VLSI Chip for Modeling Amino Acid Sequence in ProteinsS. Mitra, S. Das, Parimal Pal Chaudhuri, S. Nandi. 316-317 [doi]
• VLSI Implementation of Artificial Neural Network Based Digital Multiplier and AdderRanjeet Ranade, Sanjay Bhandari, A. N. Chandorkar. 318-319 [doi]
• Cellular automata based architecture of a database query processorSantanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri. 320-321 [doi]
• A multiplier generator for Xilinx FPGAsJaswinder Pal Singh, A. Kumar, Sanjeev Kumar. 322-323 [doi]
• Estimation of Power from Module-level NetlistsC. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora. 324-325 [doi]
• Instruction Level Power Analysis and Optimization of SoftwareVivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee. 326-328 [doi]
• Challenges in Low Power Microprocessor DesignSuresh Rajgopal. 329-330 [doi]
• An Enhanced Macromodel for a CMOS Operational Amplifier for HDL ImplementationSudhir Aggarwal. 331-332 [doi]
• KANSYS: a CAD tool for analog circuit synthesisS. K. Gupta, M. M. Hasan. 333-334 [doi]
• Dual rail static CMOS architecture for wave pipeliningG. Enrique Fernandez, R. Sridhar. 335-336 [doi]
• Syndrome signature in output compaction for VLSI BISTSunil R. Das, N. Goel, Wen-Ben Jone, A. R. Nayak. 337-338 [doi]
• Multilevel Factorization Technique for Pass Transistor LogicArunita Jaekel, Graham A. Jullien, Subir Bandyopadhyay. 339-340 [doi]
• Characteristic polynomial method for verification and test of combinational circuitsVishwani D. Agrawal, David Lee. 341-342 [doi]
• SUBGEN: a genetic approach for subcircuit extractionNarayanan Vijaykrishnan, N. Ranganathan. 343-345 [doi]
• Wiresizing with Buffer Placement and Sizing for Power-Delay TradeoffsJatan C. Shah, Sachin S. Sapatnekar. 346-351 [doi]
• Ultra low power digital signal processingAnantha Chandrakasan. 352-357 [doi]
• A low power video encoder with power, memory and bandwidth scalabilityNavin Chaddha, Mohan Vishwanath. 358-363 [doi]
• Maximum power estimation for CMOS circuits using deterministic and statistic approachesChuan-Yu Wang, Kaushik Roy. 364-369 [doi]
• Low power realization of FIR filters using multirate architecturesMahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh. 370-375 [doi]
• Self timed division and square-root extractionAlain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering. 376-381 [doi]
• Elimination of Dynamic Hazards from Signal Transition GraphsRadhakrishna Nagalla, Graham R. Hellestrand. 382-388 [doi]
• Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph SpecificationsSung-Bum Park, Takashi Nanya. 389-392 [doi]
• Multi-way partitioning of VLSI circuitsPrathima Agrawal, B. Narendran, Narayanan Shivakumar. 393-399 [doi]
• Geometric bipartitioning problem and its applications to VLSIParthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya. 400-405 [doi]
• Identifying Redundant Path Delay Faults in Sequential CircuitsRamesh C. Tekumalla, Premachandran R. Menon. 406-411 [doi]
• Diagnosis of parametric path delay faultsMukund Sivaraman, Andrzej J. Strojwas. 412-417 [doi]
• On test coverage of path delay faultsAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal. 418-421 [doi]
• Improving accuracy in path delay fault coverage estimationKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal. 422-425 [doi]
• Parallel concurrent path-delay fault simulation using single-input change patternsMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal. 426-431 [doi]
• Mobile Communications: Demands on VLSI Technology, Design and CADAnantha Chandrakasan, Kurt Keutzer, A. Khandekar, S. L. Maskara, B. D. Pradhan, Mani B. Srivastava. 432-436 [doi]