| 3273 | -- | 0 | Shinji Kimura. Special Section on VLSI Design and CAD Algorithms |
| 3274 | -- | 3281 | Hidekazu Tanaka, Koji Inoue. Adaptive Mode Control for Low-Power Caches Based on Way-Prediction Accuracy |
| 3282 | -- | 3289 | Satoshi Komatsu, Masahiro Fujita. Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications |
| 3290 | -- | 3297 | Kentaro Kawakami, Miwako Kanamori, Yasuhiro Morita, Jun Takemura, Masayuki Miyama, Masahiko Yoshimoto. Power-Minimum Frequency/Voltage Cooperative Management Method for VLSI Processor in Leakage-Dominant Technology Era |
| 3298 | -- | 3305 | Weisheng Chong, Masanori Hariyama, Michitaka Kameyama. Low-Power Field-Programmable VLSI Using Multiple Supply Voltages |
| 3306 | -- | 3314 | Ho Young Kim, Tag Gon Kim. Trace-Driven Performance Simulation Modeling for Fast Evaluation of Multimedia Processor by Simulation Reuse |
| 3315 | -- | 3323 | Takeshi Matsumoto, Hiroshi Saito, Masahiro Fujita. An Equivalence Checking Method for C Descriptions Based on Symbolic Simulation with Textual Differences |
| 3324 | -- | 3331 | Masao Morimoto, Yoshinori Tanaka, Makoto Nagata, Kazuo Taki. Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition |
| 3332 | -- | 3341 | Debatosh Debnath, Tsutomu Sasao. Exact Minimization of FPRMs for Incompletely Specified Functions by Using MTBDDs |
| 3342 | -- | 3350 | Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura. A Design Algorithm for Sequential Circuits Using LUT Rings |
| 3351 | -- | 3357 | Yuichi Nakamura, Ko Yoshikawa, Takeshi Yoshimura. An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs |
| 3358 | -- | 3366 | Hidenari Nakashima, Junpei Inoue, Kenichi Okada, Kazuya Masu. Circuit Performance Prediction Considering Core Utilization with Interconnect Length Distribution Model |
| 3367 | -- | 3374 | Zhangcai Huang, Atsushi Kurokawa, Jun Pan, Yasuaki Inoue. Modeling the Effective Capacitance of Interconnect Loads for Predicting CMOS Gate Slew |
| 3375 | -- | 3381 | Masanori Hashimoto, Tomonori Yamamoto, Hidetoshi Onodera. Statistical Analysis of Clock Skew Variation in H-Tree Structure |
| 3382 | -- | 3389 | Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto. On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design |
| 3390 | -- | 3397 | Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi. A Graph Based Soft Module Handling in Floorplan |
| 3398 | -- | 3404 | Jing Li, Juebang Yu, Hiroshi Miyashita. An Incremental Placement Algorithm for Building Block Layout Design Based on the O-Tree Representation |
| 3405 | -- | 3411 | Yongqiang Lu, Chin-Ngai Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu. Navigating Register Placement for Low Power Clock Network Design |
| 3412 | -- | 3420 | Yun Yang, Atsushi Kurokawa, Yasuaki Inoue, Wenqing Zhao. Efficient Large Scale Integration Power/Ground Network Optimization Based on Grid Genetic Algorithm |
| 3421 | -- | 3428 | Hiroyuki Tsujikawa, Kenji Shimazaki, Shozo Hirano, Kazuhiro Sato, Masanori Hirofuji, Junichi Shimada, Mitsumi Ito, Kiyohito Mukai. Power-Supply Noise Reduction with Design for Manufacturability |
| 3429 | -- | 3436 | Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera. Successive Pad Assignment for Minimizing Supply Voltage Drop |
| 3437 | -- | 3444 | Hidenari Nakashima, Naohiro Takagi, Junpei Inoue, Kenichi Okada, Kazuya Masu. Evaluation of X Architecture Using Interconnect Length Distribution |
| 3445 | -- | 3452 | Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu. Wire Length Distribution Model for System LSI |
| 3453 | -- | 3462 | Atsushi Kurokawa, Masanori Hashimoto, Akira Kasebe, Zhangcai Huang, Yun Yang, Yasuaki Inoue, Ryosuke Inagaki, Hiroo Masuda. Second-Order Polynomial Expressions for On-Chip Interconnect Capacitance |
| 3463 | -- | 3470 | Toshiki Kanamoto, Tetsuya Watanabe, Mitsutoshi Shirota, Masayuki Terai, Tatsuya Kunikiyo, Kiyoshi Ishikawa, Yoshihide Ajioka, Yasutaka Horiba. A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures |
| 3471 | -- | 3478 | Atsushi Kurokawa, Toshiki Kanamoto, Tetsuya Ibe, Akira Kasebe, Wei Fong Chang, Tetsuro Kage, Yasuaki Inoue, Hiroo Masuda. Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills |
| 3479 | -- | 3484 | Esteban Tlelo-Cuautle, Delia Torres-Muñoz, Leticia Torres-Papaqui. On the Computational Synthesis of CMOS Voltage Followers |
| 3485 | -- | 3491 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada. Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells |
| 3492 | -- | 3499 | Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto. A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application |
| 3500 | -- | 3507 | Chi-Chia Sung, Shanq-Jang Ruan, Bo-Yao Lin, Mon-Chau Shie. Quality and Power Efficient Architecture for the Discrete Cosine Transform |
| 3508 | -- | 3515 | Gab-Cheon Jung, Seong-Mo Park. VLSI Implementation of Lifting Wavelet Transform of JPEG2000 with Efficient RPA(Recursive Pyramid Algorithm) Realization |
| 3516 | -- | 3522 | Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama. FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture |
| 3523 | -- | 3530 | Zhenyu Liu, Yang Song, Takeshi Ikenaga, Satoshi Goto. A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation |
| 3531 | -- | 3538 | Yuan-Long Jeang, Jer Min Jou, Win-Hsien Huang. A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC) |
| 3539 | -- | 3547 | Luca Fanucci, Massimo Rovini, Nicola E. L Insalata, Francesco Rossi. High-Throughput Multi-Rate Decoding of Structured Low-Density Parity-Check Codes |
| 3548 | -- | 3553 | Vasily G. Moshnyaga, Tomoyuki Yamanaka. Multiplier Energy Reduction by Dynamic Voltage Variation |
| 3554 | -- | 3563 | Pao-Lung Chen, Chen-Yi Lee. A Standard Cell-Based Frequency Synthesizer with Dynamic Frequency Counting |
| 3564 | -- | 3572 | Atsushi Muramatsu, Masanori Hashimoto, Hidetoshi Onodera. Effects of On-Chip Inductance on Power Distribution Grid |
| 3573 | -- | 3576 | Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng. Perturbation Approach for Order Selections of Two-Sided Oblique Projection-Based Interconnect Reductions |
| 3577 | -- | 3579 | Hossein Shamsi, Omid Shoaei. A Simplified Illustration of Arbitrary DAC Waveform Effects in Continuous Time Delta-Sigma Modulators |
| 3580 | -- | 3583 | Chun-Lung Hsu, Wen-Tso Wang, Ying-Fu Hong. Frequency-Scaling Approach for Managing Power Consumption in NOCs |
| 3584 | -- | 3592 | Marie Nakazawa, Atsuhiro Nishikata. Development of Sound Localization System with Tube Earphone Using Human Head Model with Ear Canal |
| 3593 | -- | 3603 | Shoko Araki, Shoji Makino, Robert Aichner, Tsuyoki Nishikawa, Hiroshi Saruwatari. Subband-Based Blind Separation for Convolutive Mixtures of Speech |
| 3604 | -- | 3609 | Ho-Lim Choi, Jong-Tae Lim. Global Asymptotic Stabilization of a Class of Nonlinear Time-Delay Systems by Output Feedback |
| 3610 | -- | 3617 | Marcelo E. Kaihara, Naofumi Takagi. A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm |
| 3618 | -- | 3626 | HeeSoo Kim, Shigeru Yamada, DongHo Park. Bayesian Approach to Optimal Release Policy of Software System |
| 3627 | -- | 3635 | Hachiro Fujita, Kohichi Sakaniwa. Some Classes of Quasi-Cyclic LDPC Codes: Properties and Efficient Encoding Method |
| 3636 | -- | 3644 | Daiyuan Peng, Pingzhi Fan, Naoki Suehiro. Bounds on Aperiodic Autocorrelation and Crosscorrelation of Binary LCZ/ZCZ Sequences |
| 3645 | -- | 3653 | Weixing Bi, XuGang Wang, Zheng Tang, Hiroki Tamura. Avoiding the Local Minima Problem in Backpropagation Algorithm with Modified Error Function |
| 3654 | -- | 3657 | Hing-Cheung So. On Linear Least Squares Approach for Phase Estimation of Real Sinusoidal Signals |
| 3658 | -- | 3660 | Younseok Choo. On the Property of a Discrete Impulse Response Gramian with Application to Model Reduction |
| 3661 | -- | 3662 | Kohsuke Ogata, Toshinori Yamada, Shuichi Ueno. A Note on the Implementation of de Bruijn Networks by the Optical Transpose Interconnection System |
| 3663 | -- | 3667 | Xinpeng Zhang, Shuozhong Wang. Stego-Encoding with Error Correction Capability |
| 3668 | -- | 3671 | Mitsuhiro Hattori, Shoichi Hirose, Susumu Yoshida. Complexity of Differential Attacks on SHA-0 with Various Message Schedules |
| 3672 | -- | 3674 | Jinsoo Bae, Hiroyuki Morikawa. A Step-by-Step Implementation Method of the Bit-Serial Reed-Solomon Encoder |
| 3675 | -- | 3676 | Fanxin Zeng. Properties of m-Sequence and Construction of Constant Weight Codes |
| 3677 | -- | 3680 | Jaesang Lim, Yongchul Song, Jeong Pyo Kim, Beomsup Kim. An Efficient Software-Defined Radio Architecture for Multi-Mode WCDMA Applications |