Nadine Azémard - researchr alias

researchr

You are not signed in
Sign in
Sign up

2011

Timing slack monitoring under process and environmental variations: Application to a DSP performance optimizationBettina Rebaud, Marc Belleville, Edith Beigné, Christian Bernard, Michel Robert, Philippe Maurine, Nadine Azémard. mj, 42(5):718-732, 2011. [doi]

2010

Selected Peer-Reviewed Articles from the VARI 2010 WorkshopNadine Azémard. jolpe, 6(4):563, 2010. [doi]

On-Chip Process Variability Monitoring FlowNabila Moubdi, Philippe Maurine, Robin Wilson, Sylvain Engels, Nadine Azémard, Vincent Dumettier, Pierre Busson. jolpe, 6(4):601-606, 2010. [doi]

2009

Timing margin evaluation with a simple statistical timing analysis flowV. Migairou, Robin Wilson, Sylvain Engels, Zequin Wu, Nadine Azémard, Philippe Maurine. jec, 3(3):221-229, 2009. [doi]

2008

EditorialNadine Azémard, Philippe Maurine, Johan Vounckx. integration, 41(1):1, 2008. [doi]

Setup and Hold Timing Violations Induced by Process Variations, in a Digital MultiplierBettina Rebaud, Marc Belleville, Christian Bernard, Zequin Wu, Michel Robert, Philippe Maurine, Nadine Azémard. isvlsi 2008: 316-321 [doi]

2007

2006

A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effectsS. Engels, Robin Wilson, Nadine Azémard, Philippe Maurine. integration, 39(4):433-456, 2006. [doi]

Logical effort model extension to propagation delay representationB. Lasbouygues, S. Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne. tcad, 25(9):1677-1684, 2006. [doi]

Timing analysis in presence of supply voltage and temperature variationsB. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine. ispd 2006: 10-16 [doi]

Statistical Characterization of Library Timing PerformanceV. Migairou, Robin Wilson, S. Engels, Nadine Azémard, Philippe Maurine. patmos 2006: 468-476 [doi]

Circuit sizing method under delay constraintAlexandre Verle, A. Landrault, Philippe Maurine, Nadine Azémard. iscas 2006: [doi]

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, ProceedingsJohan Vounckx, Nadine Azémard, Philippe Maurine, editors, Volume 4148 of Lecture Notes in Computer Science, Springer, 2006.

2005

2004

2003

Metric Definition for Circuit Speed OptimizationXavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne. patmos 2003: 451-460 [doi]

CMOS Gate Sizing under Delay ConstraintAlexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne. patmos 2003: 60-69 [doi]

2002

2001

Delay bound determination for timing closure satisfactionNadine Azémard, M. Aline, Daniel Auvergne. iscas 2001: 375-378 [doi]

Feasible Delay Bound DefinitionNadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne. ifip10-5 2002: 325-335

Gate Sizing for Low Power DesignPhilippe Maurine, Nadine Azémard, Daniel Auvergne. ifip10-5 2002: 301-312

1995

Explicit evaluation of short circuit power dissipation for CMOS logic structuresS. Turgis, Nadine Azémard, Daniel Auvergne. islped 1995: 129-134 [doi]