Table of Contents

• Flow engineering for physical implementation: theory and practiceSteve Golson, Pete Churchill. 1 [doi]
• Sparse matrix computations on manycore GPU sMichael Garland. 2-6 [doi]
• Parallel programming: can we PLEASE get it right this time?Tim Mattson, Michael Wrinn. 7-11 [doi]
• Parallelizing CAD: a timely research agenda for EDABryan C. Catanzaro, Kurt Keutzer, Bor-Yiing Su. 12-17 [doi]
• Functionally linear decomposition and synthesis of logic circuits for FPGAsTomasz S. Czajkowski, Stephen Dean Brown. 18-23 [doi]
• FPGA area reduction by multi-output function based sequential resynthesisYu Hu, Victor Shih, Rupak Majumdar, Lei He. 24-29 [doi]
• A generalized network flow based algorithm for power-aware FPGA memory mappingTien-Yuan Hsu, Ting-Chi Wang. 30-33 [doi]
• Enhancing timing-driven FPGA placement for pipelined netlistsKenneth Eguro, Scott Hauck. 34-37 [doi]
• Statistical regression for efficient high-dimensional modeling of analog and mixed-signal performance variationsXin Li, Hongzhou Liu. 38-43 [doi]
• Topology synthesis of analog circuits based on adaptively generated building blocksAngan Das, Ranga Vemuri. 44-49 [doi]
• Analog placement based on hierarchical module clusteringPo-Hung Lin, Shyh-Chang Lin. 50-55 [doi]
• Run-time instruction set selection in a transmutable embedded processorLars Bauer, Muhammad Shafique, Jörg Henkel. 56-61 [doi]
• Rapid application specific floating-point unit generation with bit-alignmentYee Jern Chong, Sri Parameswaran. 62-67 [doi]
• Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiencyHouman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum. 68-71 [doi]
• C-based design flow: a case study on G.729A for voice over internet protocol (VoIP)Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski. 72-75 [doi]
• Election year: what the electronics industry needs---and can expect---from the incoming administrationTiffany Sparks, Pete Weitzner, Luc Burgun, Russell Lefevre, Todd Cutler, Clayton Parker, Vicki Hadfield, Chris Rowen. 76-77 [doi]
• A 242mW, 10mm:::2:::1080p H.264/AVC high profile encoder chipYu-Kun Lin, De-Wei Li, Chia-Chun Lin, Tzu-Yun Kuo, Sian-Jin Wu, Wei-Cheng Tai, Wei-Cheng Chang, Tian-Sheuan Chang. 78-83 [doi]
• The design of a low power carbon nanotube chemical sensor systemTaeg Sang Cho, Kyeong-Jae Lee, Jing Kong, Anantha P. Chandrakasan. 84-89 [doi]
• iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processorChih-Chi Cheng, Chia-Hua Lin, Chung-Te Li, Samuel C. Chang, Liang-Gee Chen. 90-95 [doi]
• Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processorDonghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Hoi-Jun Yoo. 96-101 [doi]
• A MIPS R2000 implementationNathaniel Ross Pinckney, Thomas Barr, Michael Dayringer, Matthew McKnett, Nan Jiang, Carl Nygaard, David Money Harris, Joel Stanley, Braden Phillips. 102-107 [doi]
• Process variation tolerant SRAM array for ultra low voltage applicationsJaydeep P. Kulkarni, Keejong Kim, Sang Phill Park, Kaushik Roy. 108-113 [doi]
• PicoCube: a 1 cm:::3::: sensor node powered by harvested energyYuen-Hui Chee, Mike Koplow, Michael Mark, Nathan Pletcher, Mike Seeman, Fred Burghardt, Dan Steingart, Jan M. Rabaey, Paul K. Wright, Seth Sanders. 114-119 [doi]
• An 8x8 run-time reconfigurable FPGA embedded in a SoCSumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger. 120-125 [doi]
• Reinventing EDA with manycore processorsSachin S. Sapatnekar, Eshel Haritan, Kurt Keutzer, Anirudh Devgan, Desmond Kirkpatrick, Stephen Meier, Duaine Pryor, Tom Spyrou. 126-127 [doi]
• Multicore design is the challenge! what is the solution?Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne Wolf, Achim Nohl, Drew Wingard, Mike Muller. 128-130 [doi]
• Compositional verification of retiming and sequential optimizationsIn-Ho Moon. 131-136 [doi]
• Tunneling and slicing: towards scalable BMCMalay K. Ganai, Aarti Gupta. 137-142 [doi]
• Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluationYan Chen, Fei Xie, Jin Yang. 143-148 [doi]
• Faster symmetry discovery using sparsity of symmetriesPaul T. Darga, Karem A. Sakallah, Igor L. Markov. 149-154 [doi]
• Application-driven floorplan-aware voltage island designDipanjan Sengupta, Resve A. Saleh. 155-160 [doi]
• DeFer: deferred decision making enabled fixed-outline floorplannerJackey Z. Yan, Chris Chu. 161-166 [doi]
• Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designsZhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang. 167-172 [doi]
• Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochipsTao Xu, Krishnendu Chakrabarty. 173-178 [doi]
• Optimality and improvement of dynamic voltage scaling algorithms for multimedia applicationsZhen Cao, Brian Foo, Lei He, Mihaela van der Schaar. 179-184 [doi]
• Feedback-controlled reliability-aware power management for real-time embedded systemsRanjani Sridharan, Nikhil Gupta, Rabi N. Mahapatra. 185-190 [doi]
• Energy-optimal software partitioning in heterogeneous multiprocessor embedded systemsMichel Goraczko, Jie Liu, Dimitrios Lymberopoulos, Slobodan Matic, Bodhi Priyantha, Feng Zhao. 191-196 [doi]
• Customizing computation accelerators for extensible multi-issue processors with effective optimization techniquesYa-shuai Lü, Li Shen, Libo Huang, Zhiying Wang, Nong Xiao. 197-200 [doi]
• An automatic scratch pad memory management tool and MPEG-4 encoder case studyRogier Baert, Eddy de Greef, Erik Brockmeyer. 201-204 [doi]
• A methodology for statistical estimation of read access yield in SRAMsMohamed H. Abu-Rahma, Kinshuk Chowdhury, Joseph Wang, Zhiqin Chen, Sei Seung Yoon, Mohab Anis. 205-210 [doi]
• Automated design of self-adjusting pipelinesJieyi Long, Seda Ogrenci Memik. 211-216 [doi]
• Speedpath prediction based on learning from a small set of examplesPouria Bastani, Kip Killpack, Li-C. Wang, Eli Chiprout. 217-222 [doi]
• Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delaysYi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni. 223-226 [doi]
• Statistical waveform and current source based standard cell models for accurate timing analysisAmit Goel, Sarma B. K. Vrudhula. 227-230 [doi]
• SystemVerilog implicit port enhancements accelerate system design & verificationClifford E. Cummings. 231-236 [doi]
• Translation of an existing VMM-based SystemVerilog testbench to OVMKelly D. Larson. 237 [doi]
• WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machinesWei Dong, Peng Li, Xiaoji Ye. 238-243 [doi]
• The mixed signal optimum energy point: voltage and parallelismBrian P. Ginsburg, Anantha P. Chandrakasan. 244-249 [doi]
• Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETsChaitanya Kshirsagar, Mohamed N. El-Zeftawi, Kaustav Banerjee. 250-255 [doi]
• Assertion-based verification of a 32 thread SPARC:::TM::: CMT microprocessorBabu Turumella, Mukesh Sharma. 256-261 [doi]
• Functional test selection based on unsupervised support vector analysisOnur Guzey, Li-C. Wang, Jeremy R. Levitt, Harry Foster. 262-267 [doi]
• Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logicRichard C. Ho, Michael Theobald, Martin M. Deneroff, Ron O. Dror, Joseph Gagliardo, David E. Shaw. 268-271 [doi]
• Technology exploration for graphene nanoribbon FETsMihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram. 272-277 [doi]
• Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancementJing Li, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy. 278-283 [doi]
• A progressive-ILP based routing algorithm for cross-referencing biochipsPing-Hung Yuh, Sachin S. Sapatnekar, Chia-Lin Yang, Yao-Wen Chang. 284-289 [doi]
• High-performance timing simulation of embedded softwareJürgen Schnerr, Oliver Bringmann, Alexander Viehl, Wolfgang Rosenstiel. 290-295 [doi]
• Model checking based analysis of end-to-end latency in embedded, real-time systems with clock driftsSwarup Mohalik, A. C. Rajeev, Manoj G. Dixit, S. Ramesh, P. Vijay Suman, Paritosh K. Pandya, Shengbing Jiang. 296-299 [doi]
• Exploring locking & partitioning for predictable shared caches on multi-coresVivy Suhendra, Tulika Mitra. 300-303 [doi]
• Miss reduction in embedded processors through dynamic, power-friendly cache designGaro Bournoutian, Alex Orailoglu. 304-309 [doi]
• ESL hand-off: fact or EDA fiction?Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil Dutt, Giovanni Mancini. 310-312 [doi]
• Characterizing chip-multiprocessor variability-toleranceSebastian Herbert, Diana Marculescu. 313-318 [doi]
• Cache modeling in probabilistic execution time analysisYun Liang, Tulika Mitra. 319-324 [doi]
• Multiprocessor performance estimation using hybrid simulationLei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr. 325-330 [doi]
• Multithreaded simulation for synchronous dataflow graphsChia-Jui Hsu, José Luis Pino, Shuvra S. Bhattacharyya. 331-336 [doi]
• Design of a mask-programmable memory/multiplier array using G4-FET technologyJay B. Brockman, Sheng Li, Peter M. Kogge, Amit Kashyap, Mohammad Mojarradi. 337-338 [doi]
• Programmable logic circuits based on ambipolar CNFETM. Haykel Ben Jamaa, David Atienza, Yusuf Leblebici, Giovanni De Micheli. 339-340 [doi]
• Analog parallelism in ring-based VCOsDaeik D. Kim, Choongyeun Cho, Jonghae Kim. 341-342 [doi]
• Techniques for fully integrated intra-/inter-chip optical communicationClaudio Favi, Edoardo Charbon. 343-344 [doi]
• How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approachMin Li, Bruno Bougard, David Novo, Liesbet Van der Perre, Francky Catthoor. 345-346 [doi]
• Bounded-lifetime integrated circuitsPuneet Gupta, Andrew B. Kahng. 347-348 [doi]
• Collective computing based on swarm intelligenceSeetharam Narasimhan, Somnath Paul, Swarup Bhunia. 349-350 [doi]
• (Bio)-behavioral CADMiodrag Potkonjak, Farinaz Koushanfar. 351-352 [doi]
• Next generation wireless-multimedia devices: who is up for the challenge?Juan C. Rey, Andreas Kuehlmann, Jan M. Rabaey, Cormac Conroy, Ted Vucurevich, Ikuya Kawasaki, Tuna B. Tarim. 353-354 [doi]
• Statistical diagnosis of unmodeled systematic timing effectsPouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir. 355-360 [doi]
• Multiple defect diagnosis using no assumptions on failing pattern characteristicsXiaochun Yu, R. D. (Shawn) Blanton. 361-366 [doi]
• Precise failure localization using automated layout analysis of diagnosis candidatesWing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton. 367-372 [doi]
• IFRA: instruction footprint recording and analysis for post-silicon bug localization in processorsSung-Boem Park, Subhasish Mitra. 373-378 [doi]
• Automatic architecture refinement techniques for customizing processing elementsBita Gorjiara, Daniel Gajski. 379-384 [doi]
• Formal datapath representation and manipulation for implementing DSP transformsPeter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel. 385-390 [doi]
• Symbolic noise analysis approach to computational hardware optimizationArash Ahmadi, Mark Zwolinski. 391-396 [doi]
• Optimizing imprecise fixed-point arithmetic circuits specified by Taylor Series through arithmetic transformYu Pang, Katarzyna Radecka. 397-402 [doi]
• Parameterized timing analysis with general delay models and arbitrary variation sourcesKhaled R. Heloue, Farid N. Najm. 403-408 [doi]
• DeMOR: decentralized model order reduction of linear networks with massive portsBoyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy. 409-414 [doi]
• Stochastic integral equation solver for efficient variation-aware interconnect extractionTarek Moselhy, Luca Daniel. 415-420 [doi]
• Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnectsKi Jin Han, Madhavan Swaminathan, Ege Engin. 421-424 [doi]
• Driver waveform computation for timing analysis with multiple voltage threshold driver modelsPeter Feldmann, Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta. 425-428 [doi]
• Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoderHazem Moussa, Amer Baghdadi, Michel Jézéquel. 429-434 [doi]
• An area-efficient high-throughput hybrid interconnection network for single-chip parallel processingAydin O. Balkan, Gang Qu, Uzi Vishkin. 435-440 [doi]
• A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-ChipZhen Zhang, Alain Greiner, Sami Taktak. 441-446 [doi]
• A practical approach of memory access parallelization to exploit multiple off-chip DDR memoriesWoo-Cheol Kwon, Sungjoo Yoo, Sung-Min Hong, Byeong Min, Kyu-Myung Choi, Soo-Kwan Eo. 447-452 [doi]
• Towards a more physical approach to gate modeling for timing, noise, and powerPeter Feldmann, Soroush Abbaspour. 453-455 [doi]
• Transistor level gate modeling for accurate and fast timing, noise, and power analysisS. Raja, F. Varadi, Murat R. Becer, Joao Geada. 456-461 [doi]
• A true electrical cell model for timing, noise, and power grid verificationNoel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin. 462-467 [doi]
• Challenges in gate level modeling for delay and SI at 65nm and belowIgor Keller, King Ho Tam, Vinod Kariat. 468-473 [doi]
• Addressing library creation challenges from recent Liberty extensionsRichard Trihy. 474-479 [doi]
• SystemClick: a domain-specific framework for early exploration using functional performance modelsChristian Sauer, Matthias Gries, Hans Peter Löb. 480-485 [doi]
• Applying passive RFID system to wireless headphones for extreme low power consumptionJoon Goo Lee, Dongha Jung, Jiho Chu, Seokjoong Hwang, Jong-Kook Kim, Janam Ku, Seon Wook Kim. 486-491 [doi]
• Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systemsShreyas Sen, Vishwanath Natarajan, Rajarajan Senguttuvan, Abhijit Chatterjee. 492-497 [doi]
• Automated design of tunable impedance matching networks for reconfigurable wireless applicationsArthur Nieuwoudt, Jamil Kawa, Yehia Massoud. 498-503 [doi]
• ELIAD: efficient lithography aware detailed router with compact post-OPC printability predictionMinsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan. 504-509 [doi]
• Predictive formulae for OPC with applications to lithography-friendly routingTai-Chen Chen, Guang-Wan Liao, Yao-Wen Chang. 510-515 [doi]
• Dose map and placement co-optimization for timing yield enhancement and leakage power reductionKwangok Jeong, Andrew B. Kahng, Chul-Hong Park, Hailong Yao. 516-521 [doi]
• Design-process integration for performance-based OPC frameworkSiew-Hong Teh, Chun-Huat Heng, Arthur Tay. 522-527 [doi]
• An efficient incremental algorithm for min-area retimingJia Wang, Hai Zhou. 528-533 [doi]
• Scalable min-register retiming under timing and initializability constraintsAaron P. Hurst, Alan Mishchenko, Robert K. Brayton. 534-539 [doi]
• Merging nodes under sequential observabilityMichael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton. 540-545 [doi]
• N-variant IC design: methodology and applicationsYousra Alkabani, Farinaz Koushanfar. 546-551 [doi]
• Verifying really complex systems: on earth and beyondAndreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman. 552-553 [doi]
• Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacementXiangyu Dong, Xiaoxia Wu, Guangyu Sun, Yuan Xie, Helen Li, Yiran Chen. 554-559 [doi]
• Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDMKrishna Bharath, Ege Engin, Madhavan Swaminathan. 560-565 [doi]
• Topological routing to maximize routability for package substrateShenghua Liu, Guoqiang Chen, Tom Tong Jing, Lei He, Tianpei Zhang, Robi Dutta, Xianlong Hong. 566-569 [doi]
• Low power passive equalizer optimization using tritonic step responseLing Zhang, Wenjian Yu, Haikun Zhu, Alina Deutsch, George A. Katopis, Daniel M. Dreps, Ernest S. Kuh, Chung-Kuan Cheng. 570-573 [doi]
• Daedalus: toward composable multimedia MP-SoC designHristo Nikolov, Mark Thompson, Todor Stefanov, Andy D. Pimentel, Simon Polstra, R. Bose, Claudiu Zissulescu, Ed F. Deprettere. 574-579 [doi]
• SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral modelsChristian Haubelt, Thomas Schlichter, Joachim Keinert, Michael Meredith. 580-585 [doi]
• Specify-explore-refine (SER): from specification to implementationAndreas Gerstlauer, Junyu Peng, Dongwan Shin, Daniel Gajski, A. Nakamura, Dai Araki, Y. Nishihara. 586-591 [doi]
• Standard interfaces in mobile terminals: increasing the efficiency of device design and accelerating innovationRisto Savolainen, Tero Rissa. 592 [doi]
• Holistic pathfinding: virtual wireless chip design for advanced technology and design explorationMatt Nowak, Jose Corleto, Christopher Chun, Riko Radojcic. 593 [doi]
• Full-chip leakage analysis in nano-scale technologies: mechanisms, variation sources, and verificationTao Li, Wenjun Zhang, Zhiping Yu. 594-599 [doi]
• Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elementsSeungwhun Paik, Youngsoo Shin. 600-605 [doi]
• Input vector control for post-silicon leakage current minimization in the presence of manufacturing variabilityYousra Alkabani, Tammara Massey, Farinaz Koushanfar, Miodrag Potkonjak. 606-609 [doi]
• Leakage power-aware clock skew scheduling: converting stolen time into leakage power reductionMin Ni, Seda Ogrenci Memik. 610-613 [doi]
• Variation-adaptive feedback control for networks-on-chip with multiple clock domainsÜmit Y. Ogras, Radu Marculescu, Diana Marculescu. 614-619 [doi]
• Application mapping for chip multiprocessorsGuangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. Kandemir. 620-625 [doi]
• Concurrent topology and routing optimization in automotive network integrationMartin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich, Richard Regler, Bardo Lang. 626-629 [doi]
• A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routersMing-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai. 630-633 [doi]
• Keeping hot chips cool: are IC thermal problems hot air?Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul Franzon, Andrew Yang, Stephen V. Kosonocky. 634-635 [doi]
• Bi-decomposing large Boolean functions via interpolation and satisfiability solvingRuei-Rung Lee, Jie-Hong Roland Jiang, Wei-Lun Hung. 636-641 [doi]
• Signature based Boolean matching in the presence of don t caresAfshin Abdollahi. 642-647 [doi]
• The synthesis of robust polynomial arithmetic with stochastic logicWeikang Qian, Marc D. Riedel. 648-653 [doi]
• Automatic synthesis of clock gating logic with controlled netlist perturbationAaron P. Hurst. 654-657 [doi]
• A new paradigm for synthesis and propagation of clock gating conditionsRanan Fraer, Gila Kamhi, Muhammad K. Mhameed. 658-663 [doi]
• 3-D semiconductor s: more from MooreTed Vucurevich. 664 [doi]
• Tera-scale computing and interconnect challengesJerry Bautista. 665-667 [doi]
• Design and CAD for 3D integrated circuitsPaul D. Franzon, W. Rhett Davis, Michael Steer, Steve Lipa, Eun Chu Oh, Thor Thorolfsson, Samson Melamed, Sonali Luniya, Tad Doxsee, Stephen Berkeley, Ben Shani, Kurt Obermiller. 668-673 [doi]
• Why should we do 3D integration?Wilfried Haensch. 674-675 [doi]
• Efficient Monte Carlo based incremental statistical timing analysisVineeth Veetil, Dennis Sylvester, David Blaauw. 676-681 [doi]
• Generalized Krylov recycling methods for solution of multiple related linear equation systems in electromagnetic analysisZuochang Ye, Zhenhai Zhu, Joel R. Phillips. 682-687 [doi]
• A framework for block-based timing sensitivity analysisSanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar. 688-693 [doi]
• Accurate and analytical statistical spatial correlation modeling for VLSI DFM applicationsJui-Hsiang Liu, Ming-Feng Tsai, Lumdo Chen, Charlie Chung-Ping Chen. 694-697 [doi]
• Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distributionMasanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu. 698-701 [doi]
• An integrated nonlinear placement framework with congestion and porosity aware buffer planningTung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan. 702-707 [doi]
• Circuit-wise buffer insertion and gate sizing algorithm with scalabilityZhanyuan Jiang, Weiping Shi. 708-713 [doi]
• Type-matching clock tree for zero skew clock gatingChia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu. 714-719 [doi]
• Robust chip-level clock tree synthesis for SOC designsAnand Rajaram, David Z. Pan. 720-723 [doi]
• Path smoothing via discrete optimizationMichael D. Moffitt, David A. Papa, Zhuo Li, Charles J. Alpert. 724-727 [doi]
• Stochastic modeling of a thermally-managed multi-core systemHwisung Jung, Peng Rong, Massoud Pedram. 728-733 [doi]
• Predictive dynamic thermal management for multicore systemsInchoon Yeo, Chih Chun Liu, Eun Jung Kim. 734-739 [doi]
• Control theory-based DVS for interactive 3D gamesYan Gu, Samarjit Chakraborty. 740-745 [doi]
• Many-core design from a thermal perspectiveWei Huang, Mircea R. Stan, Karthik Sankaranarayanan, Robert J. Ribando, Kevin Skadron. 746-749 [doi]
• Compiler-driven register re-assignment for register file power-density and temperature reductionXiangrong Zhou, Chenjie Yu, Peter Petrov. 750-753 [doi]
• MAPS: an integrated framework for MPSoC application parallelizationJianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda. 754-759 [doi]
• ADAM: run-time agent-based distributed application mapping for on-chip communicationMohammad Abdullah Al Faruque, Rudolf Krist, Jörg Henkel. 760-765 [doi]
• Latency and bandwidth efficient communication through system customization for embedded multiprocessorsChenjie Yu, Peter Petrov. 766-771 [doi]
• Federation: repurposing scalar cores for out-of-order instruction issueDavid Tarjan, Michael Boyer, Kevin Skadron. 772-775 [doi]
• ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessorPo-Chun Chang, I-Wei Wu, Jean Jyh-Jiun Shann, Chung-Ping Chung. 776-779 [doi]
• A practical reconfigurable hardware accelerator for Boolean satisfiability solversJohn D. Davis, Zhangxi Tan, Fang Yu, Lintao Zhang. 780-785 [doi]
• Reconfigurable computing using content addressable memory for improved performance and resource usageSomnath Paul, Swarup Bhunia. 786-791 [doi]
• Automated transistor sizing for FPGA architecture explorationIan Kuon, Jonathan Rose. 792-795 [doi]
• TuneFPGA: post-silicon tuning of dual-Vdd FPGAsStephen Bijansky, Adnan Aziz. 796-799 [doi]
• Strategies for mainstream usage of formal verificationRaj S. Mitra. 800-805 [doi]
• Pre-RTL formal verification: an intel experienceRobert Beers. 806-811 [doi]
• Challenges in using system-level models for RTL verificationKelvin Ng. 812-815 [doi]
• Leveraging sequential equivalence checking to enable system-level to RTL flowsPascal Urard, Asma Maalej, Roberto Guizzetti, Nitin Chawla. 816-821 [doi]
• Towards acceleration of fault simulation using graphics processing unitsKanupriya Gulati, Sunil P. Khatri. 822-827 [doi]
• Scan chain clustering for test power reductionMelanie Elm, Hans-Joachim Wunderlich, Michael E. Imhof, Christian G. Zoellin, Jens Leenstra, Nicolas Mäding. 828-833 [doi]
• On reliable modular testing with vulnerable test access mechanismsLin Huang, Feng Yuan, Qiang Xu. 834-839 [doi]
• On tests to detect via opens in digital CMOS circuitsSudhakar M. Reddy, Irith Pomeranz, Chen Liu. 840-845 [doi]
• Protecting bus-based hardware IP by secret sharingJarrod A. Roy, Farinaz Koushanfar, Igor L. Markov. 846-851 [doi]
• Design of high performance pattern matching engine through compact deterministic finite automataPiti Piyachon, Yan Luo. 852-857 [doi]
• SHIELD: a software hardware design methodology for security and reliability of MPSoCsKrutartha Patel, Sri Parameswaran. 858-861 [doi]
• A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular bufferYi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang. 862-865 [doi]
• An embedded infrastructure of debug and trace interface for the DSP platformMing-Chang Hsieh, Chih-Tsun Huang. 866-871 [doi]
• IntellBatt: towards smarter battery designSuman Kalyan Mandal, Praveen Bhojwani, Saraju P. Mohanty, Rabi N. Mahapatra. 872-877 [doi]
• A power and temperature aware DRAM architectureSong Liu, Seda Ogrenci Memik, Yu Zhang, Gokhan Memik. 878-883 [doi]
• Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scalingMasanori Kurimoto, Hiroaki Suzuki, Rei Akiyama, Tadao Yamanaka, Haruyuki Ohkuma, Hidehiro Takata, Hirofumi Shinohara. 884-889 [doi]
• Temperature management in multiprocessor SoCs using online learningAyse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross. 890-893 [doi]
• DVFS in loop accelerators using BLADESGanesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David Bull. 894-897 [doi]
• DFM in practice: hit or hype?Juan C. Rey, N. S. Nagaraj, Andrew B. Kahng, Fabian Klass, Rob Aitken, Cliff Hou, Luigi Capodieci, Vivek Singh. 898-899 [doi]
• Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughnessYun Ye, Frank Liu, Sani R. Nassif, Yu Cao. 900-905 [doi]
• Efficient algorithm for the computation of on-chip capacitance sensitivities with respect to a large set of parametersTarek A. El-Moselhy, Ibrahim M. Elfadel, David Widiger. 906-911 [doi]
• Leakage power reduction using stress-enhanced layoutsVivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal. 912-917 [doi]
• A fast, analytical estimator for the SEU-induced pulse width in combinational designsRajesh Garg, Charu Nagpal, Sunil P. Khatri. 918-923 [doi]
• On the role of timing masking in reliable logic circuit designSmita Krishnaswamy, Igor L. Markov, John P. Hayes. 924-929 [doi]
• Study of the effects of MBUs on the reliability of a 150 nm SRAM deviceJuan Antonio Maestro, Pedro Reviriego. 930-935 [doi]
• Partial order reduction for scalable testing of systemC TLM designsSudipta Kundu, Malay K. Ganai, Rajesh Gupta. 936-941 [doi]
• Construction of concrete verification models from C++Malay Haldar, Gagandeep Singh, Saurabh Prabhakar, Basant Dwivedi, Antara Ghosh. 942-947 [doi]
• Predictive runtime verification of multi-processor SoCs in SystemCAlper Sen, Vinit Ogale, Magdy S. Abadir. 948-953 [doi]
• Automated hardware-independent scenario identificationJuan Hamers, Lieven Eeckhout. 954-959 [doi]
• Predictive design space exploration using genetically programmed response surfacesHenry Cook, Kevin Skadron. 960-965 [doi]
• Efficient system design space exploration using machine learning techniquesBerkin Özisikyilmaz, Gokhan Memik, Alok N. Choudhary. 966-969 [doi]
• Improve simulation efficiency using statistical benchmark subsetting: an ImplantBench case studyZhanpeng Jin, Allen C. Cheng. 970-973 [doi]
• Modeling crosstalk in statistical static timing analysisRavikishore Gandikota, David Blaauw, Dennis Sylvester. 974-979 [doi]
• Power gating scheduling for power/ground noise reductionHailin Jiang, Malgorzata Marek-Sadowska. 980-985 [doi]
• Forbidden transition free crosstalk avoidance CODEC designChunjie Duan, Chengyu Zhu, Sunil P. Khatri. 986-991 [doi]
• Custom is from Venus and synthesis from MarsRuchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye. 992 [doi]